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Hi, Everyone, I have a question about C6711 DSK clock signal, please help me on it: In C6711DSK board, a 25MHz crystal, two ICS501(PLL clock multiplier) and a LVTH125 are used to generate the 3.3V clock signals for DSP(150MHz) and EMIF(100MHz). Why TI not directly use two 3.3V crystal oscillators (one 150MHz, one 100MHz) for DSP and EMIF? Thanks for your answers, David

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David- > I have a question about C6711 DSK clock signal, please help me on it: > > In C6711DSK board, a 25MHz crystal, two ICS501(PLL clock multiplier) and a > LVTH125 are used to generate the 3.3V clock signals for DSP(150MHz) and > EMIF(100MHz). Why TI not directly use two 3.3V crystal oscillators (one > 150MHz, one 100MHz) for DSP and EMIF? Maybe they want the 2 clocks to be synchronized or at least "in phase" every 40 nsec? Also I might guess that the SDRAM devices on the DSK board cannot run at 150 MHz; i.e access time too slow, too much cost for faster devices, etc. Jeff Brower DSP sw/hw engineer Signalogic

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>Hi, Everyone, > >I have a question about C6711 DSK clock signal, please help me on it: > >In C6711DSK board, a 25MHz crystal, two ICS501(PLL clock multiplier) and a >LVTH125 are used to generate the 3.3V clock signals for DSP(150MHz) and >EMIF(100MHz). Why TI not directly use two 3.3V crystal oscillators (one >150MHz, one 100MHz) for DSP and EMIF? Because two crystal oscs as that frequency is more expensive than one lower frequency+PLLs+buffer? Or so they can change the frequency for debugging purposes when the memory interface doesn;t work :-) Cheers, Martin -- Martin Thompson BEng(Hons) CEng MIEE TRW Conekt Stratford Road, Solihull, B90 4GW. UK Tel: +44 (0)121-627-3569 -

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