Thanks sagar for your suggestion

We are in the process of evolving interface definition between FPGA and
DSP(C6474)

I am seeing two possibility

1.     Rapid IO

2.     OBSAI

Can you please comment?

Regards
S Manimaran

From: sagar [mailto:s...@yahoo.co.in]
Sent: Monday, February 08, 2010 11:27 AM
To: Manimaran Subramanian - ERS, HCL Tech
Cc: c...@yahoogroups.com
Subject: Re: [c6x] C64x+: GSM Receiver Implementation on C64x+

Hi Subramanian,
Typical number of IQ samples required is 2. Of course it depends on your
algorithm and complexity.
I didnt get the 2 question.
How you interfaced your DSP with FPGA??Your GSM burst will be coming
continuously..so how you take into dsp by ping pong buffering?? It all depends
on how you interfaced your DSP with FPGA. Actually taking into FPGA and Framing
will be done according to your interface and send to DSP.

--- On Thu, 4/2/10, Manimaran Subramanian - ERS, HCL Tech <s...@hcl.in>
wrote:

From: Manimaran Subramanian - ERS, HCL Tech <s...@hcl.in>
Subject: [c6x] C64x+: GSM Receiver Implementation on C64x+
To: "c...@yahoogroups.com" <c...@yahoogroups.com>
Date: Thursday, 4 February, 2010, 4:31 PM

Dear All

I am in the process of capturing requirements for GSM receiver using C64X+ and 
DSP needs to be interfaced with FPGA to get an IQ samples.

Question:

 1.  What is the typical number of IQ samples required (i.e., number of samples
per symbol in the burst) i.e., decimation factor
 2.  What is the suitable interface to receive 30+ duplex channels (Rapid IO or
OBSAI)
 3.  What is the typical implementation for holding IQ samples. I.e, whether
FPGA holds number of IQ samples and transfer or DSP receives as an when IQ
samples are arrived. I believe the second implementation requires processor
attention each time.

Please clarify my doubts or tell me the pointer where I can get the details.

Thanks in advance.

Regards
S Manimaran

_____________________________________

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Hi Subramanian,
It all depends on how many channels you are processing and what is your sam=
pling rate and with how many bits you are representing your each I & Q
samp=
le. I didnt worked on 6474 so i dont have any idea of what are the peripher=
als and the data rate they support on the 6474.=20
Suppose i am handling 2 channels so gsm data rate 270.833 if i am getting u=
psampled by 2 and each sample represents by 16 samples so it comes like 270=
.833*2*16=3D8.667 Mhz so if ur I&Q is interleaved it comes arround
17.333Mh=
z. So look into how many channels ur handling and with what sampling rate a=
nd number of bits.

best regards

--- On Mon, 8/2/10, Manimaran Subramanian - ERS, HCL Tech <smanimaran@hcl.i=
n> wrote:

From: Manimaran Subramanian - ERS, HCL Tech <s...@hcl.in>
Subject: RE: [c6x] C64x+:  GSM Receiver Implementation on C64x+
To: "sagar" <s...@yahoo.co.in>
Cc: "c...@yahoogroups.com" <c...@yahoogroups.com>
Date: Monday, 8 February, 2010, 11:50 AM

=20
=20

Thanks
sagar for your suggestion=20

 =C2=A0=20

We
are in the process of evolving interface definition between FPGA and DSP(C6=
474)=20

 =C2=A0=20

I
am seeing two possibility=20

1.=C2=A0=C2=A0=C2=A0=C2=A0
Rapid
IO=20

2.=C2=A0=C2=A0=C2=A0=C2=A0
OBSAI=20

 =C2=A0=20

Can
you please comment?=20=20

 =C2=A0=20

Regards=20

S Manimaran=20

 =C2=A0=20

From: sagar
[mailto:s...@yahoo.co.in]=20

Sent: Monday, February 08, 2010 11:27 AM

To: Manimaran Subramanian - ERS, HCL Tech

Cc: c...@yahoogroups.com

Subject: Re: [c6x] C64x+: GSM Receiver Implementation on C64x+=20

 =C2=A0=20
=20
=20=20
  Hi Subramanian,

  Typical number of IQ samples required is 2. Of course it depends on your
  algorithm and complexity.

  I didnt get the 2 question.

  How you interfaced your DSP with FPGA??Your GSM burst will be coming
  continuously..so how you take into dsp by ping pong buffering?? It all
  depends on how you interfaced your DSP with FPGA. Actually taking into FP=
GA
  and Framing will be done according to your interface and send to DSP.=20

=20=20

  --- On Thu, 4/2/10, Manimaran Subramanian - ERS, HCL Tech <smanimaran@hcl=
.in>
  wrote:=20
=20=20

  From: Manimaran Subramanian - ERS, HCL Tech <s...@hcl.in>

  Subject: [c6x] C64x+: GSM Receiver Implementation on C64x+

  To: "c...@yahoogroups.com" <c...@yahoogroups.com>

  Date: Thursday, 4 February, 2010, 4:31 PM=20
=20=20
  =C2=A0=20=20
=20=20
=20=20
=20=20
=20=20
  Dear
  All=20
=20=20
=20=20
  =C2=A0=20
=20=20
=20=20
  I
  am in the process of capturing requirements for GSM receiver using C64X+
  and=C2=A0 DSP needs to be interfaced with FPGA to get an IQ samples.=20
=20=20
=20=20
  =C2=A0=20
=20=20
=20=20
  Question:=20
=20=20
=20=20
   What is the typical number of IQ samples required
       (i.e., number of samples per symbol in the burst) i.e., decimation
       factor=20
   What is the suitable interface to receive 30+
       duplex channels (Rapid IO or OBSAI)=20
   What is the typical implementation for holding IQ
       samples. I.e, whether FPGA holds number of IQ samples and transfer o=
r
       DSP receives as an when IQ samples are arrived. I believe the second
       implementation requires processor attention each time.=20
=20=20
=20=20
  =C2=A0=20
=20=20
=20=20
  Please
  clarify my doubts or tell me the pointer where I can get the details.=20
=20=20
=20=20
  =C2=A0=20
=20=20
=20=20
  Thanks
  in advance.=20
=20=20
=20=20
  =C2=A0=20
=20=20
=20=20
  Regards=20

  S Manimaran=20
=20=20

_____________________________________

______________________________
New Code Sharing Section now Live on DSPRelated.com. Learn about the Reward Program for Contributors here.



(You need to be a member of c6x -- send a blank email to c6x-subscribe@yahoogroups.com )