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Hello c6x, For a strange type of software I created a software that read from a MCBSP the Hsync of a VGA board. The scope of this software is to calculate the HSYNC time ... This signal is 66KHZ on my VGA set as 1240x768 64Mcolours To receive this signal I wrote this code void task(void) { LgUns time; LgUns prevtime; Uint32 x; do { while(!MCBSP_rrdy(hMcbsp0)); x = MCBSP_read(hMcbsp0); LOG_printf(&trace, "0x%x", x); } while(x<128); prevtime = CLK_gethtime() / counts_per_us; // FIRST time while (1) { if(MCBSP_rrdy(hMcbsp0)) { x = MCBSP_read(hMcbsp0); LOG_printf(&trace, "0x%x", x); if(x>=128) { time = CLK_gethtime() / counts_per_us; if(time<prevtime) LOG_printf(&trace, "%ld uS", (0xffffffff-prevtime)+time); else LOG_printf(&trace, "%ld uS", time-prevtime); prevtime=time; } } } } On a DSK board the sample rate generator is set : MCBSP_MK_SRGR( MCBSP_SRGR_CLKGDV_OF(0), // Clock divider MCBSP_SRGR_FWID_OF(0), // Frame width MCBSP_SRGR_FPER_OF(7), // Period MCBSP_SRGR_FSGM_FSG, // MCBSP_SRGR_CLKSM_INTERNAL, MCBSP_SRGR_CLKSP_RISING, MCBSP_SRGR_GSYNC_FREE ), The sample rate is 75 MHZ (CLGDVG = 1) The result of this routine is 39515915 0xff 39515916 16 uS 39515917 0x0 39515918 0x0 39515919 0x0 39515920 0x0 39515921 0x0 39515922 0x0 39515923 0x0 39515924 0x0 39515925 0x0 39515926 0x0 39515927 0x0 39515928 0x0 39515929 0xff 39515930 16 uS 39515931 0x0 39515932 0x0 39515933 0x0 39515934 0x0 39515935 0x0 39515936 0x0 39515937 0x0 39515938 0x0 39515939 0x0 39515940 0x0 39515941 0x0 39515942 0x0 39515943 0x0 39515944 0xff 39515945 16 uS 39515915 0xff 39515916 16 uS 39515917 0x0 39515918 0x0 39515919 0x0 39515920 0x0 39515921 0x0 39515922 0x0 39515923 0x0 39515924 0x0 39515925 0x0 39515926 0x0 39515927 0x0 39515928 0x0 39515929 0xff 39515930 16 uS 39515931 0x0 39515932 0x0 39515933 0x0 39515934 0x0 39515935 0x0 39515936 0x0 39515937 0x0 39515938 0x0 39515939 0x0 39515940 0x0 39515941 0x0 39515942 0x0 39515943 0x0 39515944 0xff 39515945 16 uS 39515946 0x0 39515947 0x0 .... With a HSYNC of 66KHZ the peak2peak time is 16uS and the software measure in correct mode this time. The MCBSP receive the signal as a sequence of bits ... The SYNC signal is not a perfect square wave but : ^ 3.3v | +-+ +-+ | / | / | | / | / | |-+ +----------------------+ +------- +-------------------------------------------- 000011.000000000000000000000000011.00000000 All signal under a determinate level (3.1vf ???) are read as 0 .... over a determinate level the bits are 1. Do you known what is this level for a normal MCBSP ? -- Best regards, flavio mailto: -------------------------------------- FLAVIO BERNARDOTTI AMC Italy srl Biometric Security Engineering Department Via La Pira, 21 10028 TROFARELLO (TO) ITALY Tel. +39 11 6804011 Fax. +39 11 6804014 Dir. +39 380 7097051 Company Sites: http://www.amcitaly.net http://biotracciabilita.info Personal sites : http://www.crackinguniversity2000.it http://www.bernardotti.it

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Flavio- . . . > With a HSYNC of 66KHZ the peak2peak time is 16uS and the software > measure in correct mode this time. > The MCBSP receive the signal as a sequence of bits ... > The SYNC signal is not a perfect square wave but : > > ^ 3.3v > | +-+ +-+ > | / | / | > | / | / | > |-+ +----------------------+ +------- > +-------------------------------------------- > 000011.000000000000000000000000011.00000000 > > All signal under a determinate level (3.1vf ???) are read as 0 .... over a > determinate level the bits are 1. > Do you known what is this level for a normal MCBSP ? The question is more "normal 3.3v logic" rather than McBSP. I'm sure TI follows normal logic standards in implementing McBSPs along with all other chip peripherals. Probably anything less than 1.2 to 1.5v is going to appear as a zero. If you can use an A/D converter in your project, then you could make very accurate waveshape and timing measurements. Jeff Brower DSP sw/hw engineer Signalogic

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