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Hi I am very new to this field. I have problem understanding the LOAD command (LDB/LDH/LDW). Can you tell me what is baseR and offsetR. How are thay used and what do they specify? Asha

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Hello, > From: asha grover <> > > Hi > > I am very new to this field. I have problem understanding the LOAD > command (LDB/LDH/LDW). These instructions load a byte, a halfword (2 bytes) or a word (4 bytes) respectively into a specified register. There is also LDDW instruction which loads a doubleword (8 bytes). To determine which location in memory is to be loaded the instuction must be supplyed with an address of this location. Note that C6000 is a byte addressable machine, thus any address points to a specific byte location. > Can you tell me what is baseR and offsetR. How are thay used and what > do they specify? These two registers are used to specify the address and the offset/increment to this address. BaseR (or base address register) contans the adress of an entity to load and offsetR (or offset register) contains the displacement or modification value to this address. Sintactically, the offset register can be enclosed either in square brackets or parenthesis to denote relative (scaled) or absolute (nonscaled) address modification commensurately. Relative means here that the offset is modified as follows: for LDB it is not modified at all, for LDH it is shfted left by 1 (effectively multiplied by 2), for LDW it is shifted left by 2 and for LDDW it is shifted left by 3, thus scaled into the respective absolute offset (in byte units). An absolute offset is assumed to be already written in byte units, thus it is never shifted. The offset register is optional and can be omitted in the instruction. For example (for simplicity, all the pipeline/execute units relative stuff is omitted) MVK 100, A1 ; BaseR MVK 2, A2 ; OffsetR LDB *+A1[A2], A3 ; load byte at address 100+2=102 LDB *A1++[A2], A3 ; load byte at address 100 ; postmodify A1 = 100+2 = 102 LDB *-A1[A2], A3 ; load byte at address 102-2=100 LDB *--A1[A2], A3 ; load byte at address 100, due to ; premodification of A1=102-2 LDW *-A1[A2],A3 ; load word at address 100-4=96 LDW *++A1[A2],A3 ; load word at address 104, due to ; premodification of A1=100+4=104 MVK 8, A2 ; new OffsetR LDW *+A1(A2), A3 ; load word at 104+8=112 It is seen that ++ or -- modify the BaseR register for the next instruction, while + or - only change the address in the current instruction. &. This simple :) P.S. There are few more things left, address pre/post modification syntax, 5/15 bit immediate constant offsets, address alignment, D1/D2 units and T1/T2 data paths, unaligned memory accesses, pipeline issues, memory access wait states, but they are no more complicated than base and offset address registers. Best regards, Andrew -- Andrew V. Nesterov () Optimized TMS320C6000 DSP Software Generic Digital Design, Inc. > Asha

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