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I was looking at the asm code on the TI website for the optimized FFT algorithms. Is there an optimum size for an FFT to best utilize the resouces on board the processor, i.e. if you wanted to use only the on chip memeory? It looked from the asm files that 256 pts was able to stay on chip. Has anyone looked at this? If I take a DSK board, and am interested in real time FFT processing, what FFT size am I looking at? Thank you

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David, If you were tinking of a Complex FFT, then the appropriate size might be L1/sizeof(complex) or L2/sizeof(complex), where L1, L2 are the corresponding sizes of the caches and sizeof(complex) is 8 bytes for 2 single precision floating point vars. The other thing is that TI most probably does not have an optimum program for C6711/13, it might be optimized for C6701. Best regards, Andrew -- Andrew V. Nesterov () Optimized TMS320C6000 DSP Software Generic Digital Design, Inc. > ________________________________________________________________________ > > Date: Mon, 10 Mar 2003 17:59:42 -0000 > From: "David Halley" <> > Subject: optimum FFT size for C6711 cache system? > > I was looking at the asm code on the TI website for the optimized FFT > algorithms. Is there an optimum size for an FFT to best utilize the > resouces on board the processor, i.e. if you wanted to use only the > on chip memeory? It looked from the asm files that 256 pts was able > to stay on chip. > > Has anyone looked at this? > > If I take a DSK board, and am interested in real time FFT processing, > what FFT size am I looking at? > > Thank you

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David, See sp_fftSPxSP() in <http://focus.ti.com/docs/tool/toolfolder.jhtml?PartNumber=SPRC121 Andrew E. At 12:29 AM 3/12/2003 +0300, Andrew Nesterov wrote: >David, > >If you were tinking of a Complex FFT, then the appropriate size >might be L1/sizeof(complex) or L2/sizeof(complex), where L1, L2 >are the corresponding sizes of the caches and sizeof(complex) is >8 bytes for 2 single precision floating point vars. > >The other thing is that TI most probably does not have an optimum >program for C6711/13, it might be optimized for C6701. > >Best regards, > >Andrew > >-- >Andrew V. Nesterov () >Optimized TMS320C6000 DSP Software >Generic Digital Design, Inc. >> ________________________________________________________________________ >> >> Date: Mon, 10 Mar 2003 17:59:42 -0000 >> From: "David Halley" <> >> Subject: optimum FFT size for C6711 cache system? >> >> I was looking at the asm code on the TI website for the optimized FFT >> algorithms. Is there an optimum size for an FFT to best utilize the >> resouces on board the processor, i.e. if you wanted to use only the >> on chip memeory? It looked from the asm files that 256 pts was able >> to stay on chip. >> >> Has anyone looked at this? >> >> If I take a DSK board, and am interested in real time FFT processing, >> what FFT size am I looking at? >> >> Thank you >> >> > > >_____________________________________

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