
Technical discussions about the TI C6000 DSPs (including the c62x, c64x and c67x DSPs).
|
Hi all,
I urgently need some help about memory
stalls. I have read a lot of documentation but I still can't understand
how my code is working. I am developing a quite large program, whose more
demanding parts are assembly coded. All my code and large buffers are in
SDRAM and SRAM is configured as 3-way cache. When I count the cycles of a
particular loop (written in assembly), I obtain a higher number of cycles than I
expected. The loop is the following (interrupts are
disabled):
LOOP:
LDW .D2 *B4++,B7
||
LDW .D1 *A6++,A7
||
MPYSP .M1X A7,B7,A5
|| ADDSP .L1 A5,A8,A8 ||[A1] B .S2 LOOP ||[A1] SUB .S1 A1,1,A1 When I execute it 700 times, the number of
cycles it takes is aprox. 1500. How can that be? What's wrong?
It would be great if someone could help me and give me some guidance about where
I am 'losing' cycles.
Thank you in advance,
Miguel Yahoo! Messenger Nueva versión: Super Webcam, voz, caritas animadas, y más ¡Gratis! |
|
|
|
The problem is caused by memory bank conflict, i.e. A6 and B4 point to the same memory bank. You can make them point to different memory space or you can make one point to bank0 while the other point to bank2. Wang Tao Hi all,
I urgently need some help about memory
stalls. I have read a lot of documentation but I still can't understand
how my code is working. I am developing a quite large program, whose more
demanding parts are assembly coded. All my code and large buffers are in
SDRAM and SRAM is configured as 3-way cache. When I count the cycles of a
particular loop (written in assembly), I obtain a higher number of cycles than I
expected. The loop is the following (interrupts are
disabled):
LOOP:
LDW .D2 *B4++,B7
||
LDW .D1 *A6++,A7
||
MPYSP .M1X A7,B7,A5
|| ADDSP .L1 A5,A8,A8 ||[A1] B .S2 LOOP ||[A1] SUB .S1 A1,1,A1 When I execute it 700 times, the number of
cycles it takes is aprox. 1500. How can that be? What's wrong?
It would be great if someone could help me and give me some guidance about where
I am 'losing' cycles.
Thank you in advance,
Miguel
Yahoo! Messenger Nueva versión: Super Webcam, voz, caritas animadas, y más ¡Gratis! _____________________________________ Note: If you do a simple "reply" with your email client, only the author of this message will receive your answer. You need to do a "reply all" if you want your answer to be distributed to the entire group. _____________________________________ About this discussion group: To Join: Send an email to c...@yahoogroups.com To Post: Send an email to c...@yahoogroups.com To Leave: Send an email to c...@yahoogroups.com Archives: http://www.yahoogroups.com/group/c6x Other Groups: http://w ww.dsprelated.com Your use of Yahoo! Groups is subject to the Yahoo! Terms of Service. -- _______________________________________________ |
|
Thank you for your answer. But I don't know how to control which memory
banks my registers are pointing to, as my large buffers are placed in SDRAM and my SRAM is configured as 3-way cache. Could the problem be with L1? Thank you, Miguel ----- Original Message ----- From: Tao Wang To: José Miguel Sebastián Hernando ; Sent: Tuesday, September 23, 2003 3:10 AM Subject: Re: [c6x] Help on memory stalls!!!! The problem is caused by memory bank conflict, i.e. A6 and B4 point to the same memory bank. You can make them point to different memory space or you can make one point to bank0 while the other point to bank2. Wang Tao ----- Original Message ----- From: José Miguel Sebastián Hernando Date: Mon, 22 Sep 2003 21:01:21 +0200 (CEST) To: Subject: [c6x] Help on memory stalls!!!! Hi all, I urgently need some help about memory stalls. I have read a lot of documentation but I still can't understand how my code is working. I am developing a quite large program, whose more demanding parts are assembly coded. All my code and large buffers are in SDRAM and SRAM is configured as 3-way cache. When I count the cycles of a particular loop (written in assembly), I obtain a higher number of cycles than I expected. The loop is the following (interrupts are disabled): LOOP: LDW .D2 *B4++,B7 || LDW .D1 *A6++,A7 || MPYSP .M1X A7,B7,A5 || ADDSP .L1 A5,A8,A8 ||[A1] B .S2 LOOP ||[A1] SUB .S1 A1,1,A1 When I execute it 700 times, the number of cycles it takes is aprox. 1500. How can that be? What's wrong? It would be great if someone could help me and give me some guidance about where I am 'losing' cycles. Thank you in advance, Miguel --------------------------------- Yahoo! Messenger Nueva versión: Super Webcam, voz, caritas animadas, y más ¡Gratis! _____________________________________ Note: If you do a simple "reply" with your email client, only the author of this message will receive your answer. You need to do a "reply all" if you want your answer to be distributed to the entire group. _____________________________________ About this discussion group: To Join: Send an email to To Post: Send an email to To Leave: Send an email to Archives: http://www.yahoogroups.com/group/c6x Other Groups: http://w ww.dsprelated.com Your use of Yahoo! Groups is subject to the Yahoo! Terms of Service. -- _______________________________________________ Sign-up for your own personalized E-mail at Mail.com CareerBuilder.com has over 400,000 jobs. Be smarter about your job search --------------------------------- Yahoo! Messenger Nueva versión: Super Webcam, voz, caritas animadas, y más #161;Gratis! |
|
Yes, it is with L1. The memory bank is a concept of internal program and
data mem. You use internal data ram as cache for sdram. So your LD instruction will load data from internal data ram most of the time. I am not sure how to solve your problem. Perhaps you can make cache direct map(1-way), for your load is 4 byte, and if you align all your data on fixed bound, dsp maybe read memory on different bank. good luck Wang Tao ----- Original Message ----- From: José Miguel Sebastián Hernando <> Date: Tue, 23 Sep 2003 16:09:11 +0200 (CEST) To: Subject: Re: [c6x] Help on memory stalls!!!! Re: Thank you for your answer. But I don't know how to control which memory banks my registers are pointing to, as my large buffers are placed in SDRAM and my SRAM is configured as 3-way cache. Could the problem be with L1? Re: Re: Thank you, Re: Re: Miguel Re: Re: Re: ----- Original Message ----- Re: From: Tao Wang Re: To: José Miguel Sebastián Hernando ; Re: Sent: Tuesday, September 23, 2003 3:10 AM Re: Subject: Re: [c6x] Help on memory stalls!!!! Re: Re: Re: Re: The problem is caused by memory bank conflict, i.e. A6 and B4 point to the same memory bank. You can make them point to different memory space or you can make one point to bank0 while the other point to bank2. Re: Re: Wang Tao Re: Re: ----- Original Message ----- Re: From: José Miguel Sebastián Hernando Re: Date: Mon, 22 Sep 2003 21:01:21 +0200 (CEST) Re: To: Re: Subject: [c6x] Help on memory stalls!!!! Re: Re: Re: Hi all, Re: Re: I urgently need some help about memory stalls. I have read a lot of documentation but I still can't understand how my code is working. I am developing a quite large program, whose more demanding parts are assembly coded. All my code and large buffers are in SDRAM and SRAM is configured as 3-way cache. When I count the cycles of a particular loop (written in assembly), I obtain a higher number of cycles than I expected. The loop is the following (interrupts are disabled): Re: Re: LOOP: Re: Re: LDW .D2 *B4++,B7 Re: || LDW .D1 *A6++,A7 Re: || MPYSP .M1X A7,B7,A5 Re: || ADDSP .L1 A5,A8,A8 Re: ||[A1] B .S2 LOOP Re: ||[A1] SUB .S1 A1,1,A1 Re: Re: When I execute it 700 times, the number of cycles it takes is aprox. 1500. How can that be? What's wrong? It would be great if someone could help me and give me some guidance about where I am 'losing' cycles. Re: Re: Thank you in advance, Re: Re: Miguel Re: Re: Re: --------------------------------- Re: Yahoo! Messenger Re: Nueva versión: Super Webcam, voz, caritas animadas, y más ¡Gratis! Re: _____________________________________ Re: Re: Re: Re: Re: Re: -- __________________________________________________________ Sign-up for your own personalized E-mail at Mail.com http://www.mail.com/?sr=signup CareerBuilder.com has over 400,000 jobs. Be smarter about your job search http://corp.mail.com/careers |