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Hello all, I was reading through the DSP algorithms on the TI site, and noticed the speed degradation caused by "memory bank hits". Now, I understand that this refers to the program calling on a memory bank that is already accessed, and that loads can't be performed in parallel. I have also read about making sure variables are located at 8-byte boundaries to prevent memory bank hits. How are the memory banks arranged in a c6x? How can I make sure that my programs avoid hits? Why the 8-byte boundary? Any insight would be appreciated. Thanks. Matt

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> Message: 3 > Date: Tue, 27 Mar 2001 17:07:47 -0000 > From: "Matt" <> > Subject: Memory Bank Hits > > Hello all, Hi Matt, Take a look at the TMS320C000 Periferals Reference Guide, SPRU190, for detailed discussion on memory accesses. > I was reading through the DSP algorithms on the TI site, and > noticed the speed degradation caused by "memory bank hits". > Now, I understand that this refers to the program calling on > a memory bank that is already accessed, and that loads can't > be performed in parallel. Two ported memory allows reading/writing in parallel as long as different memory banks are accessed. Since internal memory is divided into two blocks, dual access is possible on the same bank if two different blocks are accessed in parallel. Memory hit occures when the same bank in the same block is being accessed which stalls the pipeline for 1 cycle to allow for the second access to complete. > I have also read about making sure variables are located > at 8-byte boundaries to prevent memory bank hits. This is a DWORD boundary. On C62x/67x you cannot read DWORD (by LDDW) across a DWORD boundary. But there will be still memory hit if you address the same bank by two LDDWs in parallel, e.g. on C67x 0x...00 and 0x....10 or 0x...08 and 0x....18, that is even and odd DWORDs. This rule is extended so forth to WORD (4 byte) and 1/2WORD (2 byte) -- you cannot read a WORD across WORD boundary, and 1/2WORD across a halfword boundary. Take a look at the figure 2-8 in SPRU190, although it may seem be like a chessmate board, it shows all conflicting memory accesses. Byte access (LDB/STB) is unrestricted, but stil you cannot access a byte across a bit boundary (I am joking :)). BTW, the latest in the C6x devices (C64x) probably allows unaligned memory accesses. > How are the memory banks arranged in a c6x? How can I make > sure that my programs avoid hits? Why the 8-byte boundary? Chapters 2,3,4 in the SPRU190 have detailed explanation how banks are arranged. Regards, Andrew > Any insight would be appreciated. Thanks. > > Matt

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