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Discussion Groups | TMS320C6x | External Memory Access with C64x
Technical discussions about the TI C6000 DSPs (including the c62x, c64x and c67x DSPs).
External Memory Access with C64x - cng...@lmint.com - May 5 20:00:00 2005
Hi
I am hoping to learn more about how C64x access memory with the L1/L2 cache architecture.
If I use try to read a 16-bit value (with LDH) from a non-cached region in the external SDRAM (64-bit wide), does C64x performs a 16-bit access to the SDRAM to fetch just that value? Or does it perform 64-bit reads to get 64 bytes (L1D line size) worth of data?
I did a simple test where I read-in a continguous block of memory using 16-bit access and it seems to be slower than the corresponding 32-bit/64-bit accesses. I am wondering why this is the case given that the L1D line size is 64 bytes..
Thanks
Chi Ho
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New Code Sharing Section now Live on DSPRelated.com. Learn about the Reward Program for Contributors here.
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I am hoping to learn more about how C64x access memory with the L1/L2 cache architecture.
If I use try to read a 16-bit value (with LDH) from a non-cached region in the external SDRAM (64-bit wide), does C64x performs a 16-bit access to the SDRAM to fetch just that value? Or does it perform 64-bit reads to get 64 bytes (L1D line size) worth of data?
I did a simple test where I read-in a continguous block of memory using 16-bit access and it seems to be slower than the corresponding 32-bit/64-bit accesses. I am wondering why this is the case given that the L1D line size is 64 bytes..
Thanks
Chi Ho
______________________________
New Code Sharing Section now Live on DSPRelated.com. Learn about the Reward Program for Contributors here.
(You need to be a member of c6x -- send a blank email to c6x-subscribe@yahoogroups.com )