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Hi, I am trying to write linear assembly code for C64x for the DCT/IDCT operation. The algorithm requires that an entire row/column be loaded into the register bank. Consequently I have the following statements in my code: LDH *block++(2), block0 LDH *block++(2), block1 ....... and so on. However the .asm file generated by the linear assembly optimizer shows that these memory loads are scheduled sequentially rather than in parallel. Is there any information which if passed to the linear assembly optimizer will effectively schedule the memory loads in parallel ? ANY pointer will be appreciated. Thanks and Regards, Shailendra

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I could use some help with a design I am working on. I am using the TMS320C6711B along with the MSP430F148 and two Xilinx FPGAs. I would like to use all four devices in a single JTAG chain. But I understand that this is not a good idea as the different vendor's tools will not work compatibly. Is this correct? Will I not be able to use the JTAG debugger on the TMS320C6711 and MSP430F148 if I have the Xilinx parts in the chain? I have viewed the JTAG documentation available on the TI web site. I still have not been able to determine if the JTAG debugger will operate with the Xilinx parts in the JTAG chain. I can't even tell if the TMS320C6711 and MSP430F148 will be compatible. I am not so worried about using the Xilinx tools. I don't expect to need to use the Xilinx debugger. The Xilinx chips are in the chain for boundary scan. BTW, does anyone know how to use the TI emulator as a JTAG controller for boundary scan? Is there documentation on that? Has anyone done boundary scan before? What did you use as a controller? Rick Collins Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX

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I understand. But with three separate chains I can't do boundary scan testing. I also don't have the space for it. If I have to use them separately, I will add a jumper to let me use the TMS320 or the MSP430 or all together for boundary scan. I'll have to think about that one since it seems to be important to keep all the JTAG leads very short. What good is boundary scan if no one supports it with other vendor's chips??? At 05:05 PM 1/14/02, Jeff Brower wrote: >Rick- > >If you can avoid it, I would suggest not to combine them. Just place one >JTAG >header for the C6711 and another for the Xilinx chain. The only problem with >that would be if you are really pressed for board space. > >With a combined header, if you run into small, weird problems, which >vendor is >going to help? Most likely neither. > >FWIW, normally we program Xilinx FPGAs using the "FPGA" pod, which is not >JTAG >and is some type of proprietary "byte blaster" similar to Altera. > >Jeff Brower >DSP sw/hw engineer >Signalogic > >On Mon, 14 Jan 2002, Arius - Rick Collins <> wrote: > >I could use some help with a design I am working on. I am using the > >TMS320C6711B along with the MSP430F148 and two Xilinx FPGAs. I would like > >to use all four devices in a single JTAG chain. But I understand that this > >is not a good idea as the different vendor's tools will not work compatibly. > > > >Is this correct? Will I not be able to use the JTAG debugger on the > >TMS320C6711 and MSP430F148 if I have the Xilinx parts in the chain? I have > >viewed the JTAG documentation available on the TI web site. I still have > >not been able to determine if the JTAG debugger will operate with the > >Xilinx parts in the JTAG chain. I can't even tell if the TMS320C6711 and > >MSP430F148 will be compatible. > > > >I am not so worried about using the Xilinx tools. I don't expect to need to > >use the Xilinx debugger. The Xilinx chips are in the chain for boundary > scan. > > > >BTW, does anyone know how to use the TI emulator as a JTAG controller for > >boundary scan? Is there documentation on that? Has anyone done boundary > >scan before? What did you use as a controller? > > > > > >Rick Collins > > > > > > > >Arius - A Signal Processing Solutions Company > >Specializing in DSP and FPGA design http://www.arius.com > >4 King Ave 301-682-7772 Voice > >Frederick, MD 21701-3110 301-682-7666 FAX Rick Collins Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX

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Rick- If you can avoid it, I would suggest not to combine them. Just place one JTAG header for the C6711 and another for the Xilinx chain. The only problem with that would be if you are really pressed for board space. With a combined header, if you run into small, weird problems, which vendor is going to help? Most likely neither. FWIW, normally we program Xilinx FPGAs using the "FPGA" pod, which is not JTAG and is some type of proprietary "byte blaster" similar to Altera. Jeff Brower DSP sw/hw engineer Signalogic On Mon, 14 Jan 2002, Arius - Rick Collins <> wrote: >I could use some help with a design I am working on. I am using the >TMS320C6711B along with the MSP430F148 and two Xilinx FPGAs. I would like >to use all four devices in a single JTAG chain. But I understand that this >is not a good idea as the different vendor's tools will not work compatibly. > >Is this correct? Will I not be able to use the JTAG debugger on the >TMS320C6711 and MSP430F148 if I have the Xilinx parts in the chain? I have >viewed the JTAG documentation available on the TI web site. I still have >not been able to determine if the JTAG debugger will operate with the >Xilinx parts in the JTAG chain. I can't even tell if the TMS320C6711 and >MSP430F148 will be compatible. > >I am not so worried about using the Xilinx tools. I don't expect to need to >use the Xilinx debugger. The Xilinx chips are in the chain for boundary scan. > >BTW, does anyone know how to use the TI emulator as a JTAG controller for >boundary scan? Is there documentation on that? Has anyone done boundary >scan before? What did you use as a controller? >Rick Collins > >Arius - A Signal Processing Solutions Company >Specializing in DSP and FPGA design http://www.arius.com >4 King Ave 301-682-7772 Voice >Frederick, MD 21701-3110 301-682-7666 FAX

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Rick- >I understand. But with three separate chains I can't do boundary scan >testing. I also don't have the space for it. If I have to use them >separately, I will add a jumper to let me use the TMS320 or the MSP430 or >all together for boundary scan. I'll have to think about that one since it >seems to be important to keep all the JTAG leads very short. > >What good is boundary scan if no one supports it with other vendor's chips??? Well technically they do, the question is just whether you want to mess with it or not. Question: this is a C6711 design, right? Why not just make a host port header available; why do you need BDSL? With the host port, you can hook up a simple PCI card or parallel port adapter and test the heck out of the board using some basic DSP code. That's what we do for C54xx, C6x11, and C6x01 -- once you have HPI access, you have the option for any test level up to "full functional test". Jeff Brower DSP sw/hw engineer Signalogic >At 05:05 PM 1/14/02, Jeff Brower wrote: >>Rick- >> >>If you can avoid it, I would suggest not to combine them. Just place one >>JTAG >>header for the C6711 and another for the Xilinx chain. The only problem with >>that would be if you are really pressed for board space. >> >>With a combined header, if you run into small, weird problems, which >>vendor is >>going to help? Most likely neither. >> >>FWIW, normally we program Xilinx FPGAs using the "FPGA" pod, which is not >>JTAG >>and is some type of proprietary "byte blaster" similar to Altera. >> >>Jeff Brower >>DSP sw/hw engineer >>Signalogic >> >>On Mon, 14 Jan 2002, Arius - Rick Collins <> wrote: >> >I could use some help with a design I am working on. I am using the >> >TMS320C6711B along with the MSP430F148 and two Xilinx FPGAs. I would like >> >to use all four devices in a single JTAG chain. But I understand that this >> >is not a good idea as the different vendor's tools will not work compatibly. >> > >> >Is this correct? Will I not be able to use the JTAG debugger on the >> >TMS320C6711 and MSP430F148 if I have the Xilinx parts in the chain? I have >> >viewed the JTAG documentation available on the TI web site. I still have >> >not been able to determine if the JTAG debugger will operate with the >> >Xilinx parts in the JTAG chain. I can't even tell if the TMS320C6711 and >> >MSP430F148 will be compatible. >> > >> >I am not so worried about using the Xilinx tools. I don't expect to need to >> >use the Xilinx debugger. The Xilinx chips are in the chain for boundary >> scan. >> > >> >BTW, does anyone know how to use the TI emulator as a JTAG controller for >> >boundary scan? Is there documentation on that? Has anyone done boundary >> >scan before? What did you use as a controller? >> > >> > >> >Rick Collins >> > >> > >> > >> >Arius - A Signal Processing Solutions Company >> >Specializing in DSP and FPGA design http://www.arius.com >> >4 King Ave 301-682-7772 Voice >> >Frederick, MD 21701-3110 301-682-7666 FAX > >Rick Collins > >Arius - A Signal Processing Solutions Company >Specializing in DSP and FPGA design http://www.arius.com >4 King Ave 301-682-7772 Voice >Frederick, MD 21701-3110 301-682-7666 FAX

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