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Discussion Groups | TMS320C6x | HPI preformance
Technical discussions about the TI C6000 DSPs (including the c62x, c64x and c67x DSPs).
HPI preformance - avidor.rm - Oct 11 11:39:00 2005
Hi,
I'm designing a new board that will have three tms320c6414 DSPs on it.
Two of them will encode an MPEG-4 stream, and the 3rd one will
multiplex the two encoded video streams and audio.
I'm considering connecting the DSPs throw the HPI with an FPGA in the
middle as a host.
I'm concerned regarding the actual throughput of the HPI when the two
encoder DSPs will be very active ~80% cpu usage. (I read SPRA964)
The HPI host (the FPGA) will take the encoded bitstream from the two
encoder DPSs and will put them in the 3rd DSPs.
Will this affect the encoder DSPs in such a way the will cause stalls?
Is there a better way to connect multiple DSPs?
Please consider that in a second system that I'm designing I will need
to transfer throw the HPI in the same way (using the FPGA as a host)
an uncompressed fame (i.e. ~600Kbyte).
______________________________
Start your Android Ice Cream Sandwich development on TI's AM35x Sitara ARM Cortex-A8 processor today.
(You need to be a member of c6x -- send a blank email to c6x-subscribe@yahoogroups.com )
I'm designing a new board that will have three tms320c6414 DSPs on it.
Two of them will encode an MPEG-4 stream, and the 3rd one will
multiplex the two encoded video streams and audio.
I'm considering connecting the DSPs throw the HPI with an FPGA in the
middle as a host.
I'm concerned regarding the actual throughput of the HPI when the two
encoder DSPs will be very active ~80% cpu usage. (I read SPRA964)
The HPI host (the FPGA) will take the encoded bitstream from the two
encoder DPSs and will put them in the 3rd DSPs.
Will this affect the encoder DSPs in such a way the will cause stalls?
Is there a better way to connect multiple DSPs?
Please consider that in a second system that I'm designing I will need
to transfer throw the HPI in the same way (using the FPGA as a host)
an uncompressed fame (i.e. ~600Kbyte).
______________________________
Start your Android Ice Cream Sandwich development on TI's AM35x Sitara ARM Cortex-A8 processor today.
(You need to be a member of c6x -- send a blank email to c6x-subscribe@yahoogroups.com )
Re: HPI preformance - Mike Dunn - Oct 11 12:37:00 2005
Hello avidor,
From what I understand it seems like you would connect
the two HPI ports directly to the EMIF of the third
DSP and use EDMA to transfer data.
You will need to prototype something that resembles
your system to get a an accurate idea of the overhead
involved.
mikedun
--- "avidor.rm" <avidor@avid...> wrote:
> Hi,
>
> I'm designing a new board that will have three
> tms320c6414 DSPs on it.
> Two of them will encode an MPEG-4 stream, and the
> 3rd one will
> multiplex the two encoded video streams and audio.
>
> I'm considering connecting the DSPs throw the HPI
> with an FPGA in the
> middle as a host.
>
> I'm concerned regarding the actual throughput of the
> HPI when the two
> encoder DSPs will be very active ~80% cpu usage. (I
> read SPRA964)
>
> The HPI host (the FPGA) will take the encoded
> bitstream from the two
> encoder DPSs and will put them in the 3rd DSPs.
>
> Will this affect the encoder DSPs in such a way the
> will cause stalls?
>
> Is there a better way to connect multiple DSPs?
>
> Please consider that in a second system that I'm
> designing I will need
> to transfer throw the HPI in the same way (using the
> FPGA as a host)
> an uncompressed fame (i.e. ~600Kbyte). > c6x-unsubscribe@c6x-...
______________________________
Start your Android Ice Cream Sandwich development on TI's AM35x Sitara ARM Cortex-A8 processor today.
(You need to be a member of c6x -- send a blank email to c6x-subscribe@yahoogroups.com )
From what I understand it seems like you would connect
the two HPI ports directly to the EMIF of the third
DSP and use EDMA to transfer data.
You will need to prototype something that resembles
your system to get a an accurate idea of the overhead
involved.
mikedun
--- "avidor.rm" <avidor@avid...> wrote:
> Hi,
>
> I'm designing a new board that will have three
> tms320c6414 DSPs on it.
> Two of them will encode an MPEG-4 stream, and the
> 3rd one will
> multiplex the two encoded video streams and audio.
>
> I'm considering connecting the DSPs throw the HPI
> with an FPGA in the
> middle as a host.
>
> I'm concerned regarding the actual throughput of the
> HPI when the two
> encoder DSPs will be very active ~80% cpu usage. (I
> read SPRA964)
>
> The HPI host (the FPGA) will take the encoded
> bitstream from the two
> encoder DPSs and will put them in the 3rd DSPs.
>
> Will this affect the encoder DSPs in such a way the
> will cause stalls?
>
> Is there a better way to connect multiple DSPs?
>
> Please consider that in a second system that I'm
> designing I will need
> to transfer throw the HPI in the same way (using the
> FPGA as a host)
> an uncompressed fame (i.e. ~600Kbyte). > c6x-unsubscribe@c6x-...
______________________________
Start your Android Ice Cream Sandwich development on TI's AM35x Sitara ARM Cortex-A8 processor today.
(You need to be a member of c6x -- send a blank email to c6x-subscribe@yahoogroups.com )