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Discussion Groups | TMS320C6x | Re: HPI and EDMA contention
Technical discussions about the TI C6000 DSPs (including the c62x, c64x and c67x DSPs).
Re: HPI and EDMA contention - Jeff Brower - Dec 19 9:31:00 2005
Nir-
> The destination address is 0xbf1e8. I tried "more aligned" addresses,
> like 0x70000, but I had the same problem. I even tried address in
> external memory. same there.
>
> The load I'm talikng about is low (5Mbit/sec in and out).
>
> We use cached external memory space, so this use EDMA.
> We use 2 EDMA channels to copy data in and out the DSP (from FPGA).
> We use 6 QDMA channels for transferring data from external to
> internal memory, internal to internal, and internal to external.
>
> We just saw in spraa02 that to copy data from internal to internal
> memory, we better use memcpy instead of QDMA, so we will try this and
> release one QDMA channel.
>
> Do you think that making the EDMA copies smaller (fragment one large
> copy to many small copies) can solve this? (We saw someone asking
> about HPI and EDMA contention at TI site, but no answer).
Assuming that for sure you've made the HPI DMA channel highest priority, then yes
that would be one thing to try, and another is to give some 'pause' between the
smaller copies.
Your DSP code use of DMA during normal operation is extensive. If it really turns
out that you have DMA core consuming internal memory bus bandwidth and holding off
HPI transfers, then you may need to replace a couple of those DMA channels with an
interrupt-driven function that makes the transfer. You could could control the
pacing, and this "pseudo-DMA" would be from the CPU core.
-Jeff
______________________________
New Code Sharing Section now Live on DSPRelated.com. Learn about the Reward Program for Contributors here.
(You need to be a member of c6x -- send a blank email to c6x-subscribe@yahoogroups.com )
> The destination address is 0xbf1e8. I tried "more aligned" addresses,
> like 0x70000, but I had the same problem. I even tried address in
> external memory. same there.
>
> The load I'm talikng about is low (5Mbit/sec in and out).
>
> We use cached external memory space, so this use EDMA.
> We use 2 EDMA channels to copy data in and out the DSP (from FPGA).
> We use 6 QDMA channels for transferring data from external to
> internal memory, internal to internal, and internal to external.
>
> We just saw in spraa02 that to copy data from internal to internal
> memory, we better use memcpy instead of QDMA, so we will try this and
> release one QDMA channel.
>
> Do you think that making the EDMA copies smaller (fragment one large
> copy to many small copies) can solve this? (We saw someone asking
> about HPI and EDMA contention at TI site, but no answer).
Assuming that for sure you've made the HPI DMA channel highest priority, then yes
that would be one thing to try, and another is to give some 'pause' between the
smaller copies.
Your DSP code use of DMA during normal operation is extensive. If it really turns
out that you have DMA core consuming internal memory bus bandwidth and holding off
HPI transfers, then you may need to replace a couple of those DMA channels with an
interrupt-driven function that makes the transfer. You could could control the
pacing, and this "pseudo-DMA" would be from the CPU core.
-Jeff
______________________________
New Code Sharing Section now Live on DSPRelated.com. Learn about the Reward Program for Contributors here.
(You need to be a member of c6x -- send a blank email to c6x-subscribe@yahoogroups.com )