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hello,everybody.I'm puzzzled by fetch packe(FP)t and execute packet(EP) of C64X.i think i
would get help here.there is an excerpt from my custom asemble file boot_load.asm:
_code_loop1:
            ldb   *B4++,B5
            mvkl  CODE_SIZE,B6 ;B6 = CODE_SIZE
            add   1,A1,A1          ;A1+=1,inc outer counter
      ||    mvkh  CODE_SIZE,B6       
            cmplt A1,B6,B0
            nop
            stb   B5,*A4++
      [B0]  b     _code_loop1
            nop   5            
           .ref   _c_int00        
            mvkl .S2 _c_int00, B0
            mvkh .S2 _c_int00, B0
            B    .S2 B0
            nop   5
i wonder whether my understanding about FP and EP is right.
i think we can't  determine if the consecutive instructions(less than 9 ) belong to a same FP.
A fetch packet's start address is multiple of 8,the start address is a word    (32-bit)address,
a single instruction is at random address.so we can't decide whether  two instructions are in a
same FP or  belong to two different FP.I think it's easy to decide whether sequential
instructions is in a same execute packet.two instructions connected by symbol "||" 
belong to a same EP,if not,belong to two different EP.
The above is my understanding about FP and EP,if i'm wrong,please point out and some reference
material is welcome.thank you for your time.

(You need to be a member of c6x -- send a blank email to c6x-subscribe@yahoogroups.com )

tms320dm642,
 
You are making FPs too complicated.
 
The FP logic is very simple - it always fetches an address with the lower 5 bits==0 [the
address is always a multiple of 0x020].  Address bits 4,3, and 2 select the word in the FP on a
branch.
 
Earlier c6x devices [620x, 621x, 6701, 671x] must have EPs completely contained within a FP. 
If you look at compiler generated code, you will see NOPs are used to finish out a FP when the
next EP will not fit.  This is one reason [of many] that the performance [especially tight
loops] of these devices can change significantly with the addition of a single instruction.
 
Newer devices [DM64x, c64x, c672x] support EPs spanning FPs. Your assessment of identifying EPs
is correct.

mikedunn

----- Original Message ----
From: t...@yahoo.com.cn
To: c...@yahoogroups.com
Sent: Wednesday, September 27, 2006 8:57:58 PM
Subject: [c6x] I'm puzzzled about fetch packet and execute packet

hello,everybody. I'm puzzzled by fetch packe(FP)t and execute packet(EP) of C64X.i think i
would get help here.there is an excerpt from my custom asemble file boot_load.asm:
_code_loop1:
ldb *B4++,B5
mvkl CODE_SIZE,B6 ;B6 = CODE_SIZE
add 1,A1,A1 ;A1+=1,inc outer counter
|| mvkh CODE_SIZE,B6 
cmplt A1,B6,B0
nop
stb B5,*A4++
[B0] b _code_loop1
nop 5 
.ref _c_int00 
mvkl .S2 _c_int00, B0
mvkh .S2 _c_int00, B0
B .S2 B0
nop 5
i wonder whether my understanding about FP and EP is right.
i think we can't determine if the consecutive instructions( less than 9 ) belong to a same FP.
A fetch packet's start address is multiple of 8,the start address is a word (32-bit)address, a
single instruction is at random address.so we can't decide whether two instructions are in a
same FP or belong to two different FP.I think it's easy to decide whether sequential
instructions is in a same execute packet.two instructions connected by symbol "||"
belong to a same EP,if not,belong to two different EP.
The above is my understanding about FP and EP,if i'm wrong,please point out and some reference
material is welcome.thank you for your time.
 

(You need to be a member of c6x -- send a blank email to c6x-subscribe@yahoogroups.com )