AD535 | BIOS | Booting | Bootloader | C621 | C6211 | C6415 | C671 | C6711 | C6711DSK | C6713 | CCS | Chassaing | COFF | DAT | DM64 | DM642 | DMA | DSK671 | DSK6711 | EDM | EDMA | EMIF | Emulator | EVM | EVM620 | FFT | FIR | GPIO | Halting | HPI | HWI | IDK | JTAG | LDB | LDH | LDW | Linker | LMS | LOG_printf | Matlab | McBSP | MEM_alloc | MIPS | PCI | PCM3003 | Pipeline | Profiling | QDM | Reset | ROM | RTDX | Sampling | SDRAM | Stack | TEB | THS1206 | TMS320C621 | TMS320C6416 | TMS320C6711 | TMS320C6713 | UART | Vector Table | XBUS | XDS560

Hello,

I have seen a couple of threads mentioning that FIFO can be connected
to EMIF port in synchronous mode. 

However, from TI application notes it appears that the EMIF does not
support the synchronous FIFO mode, and therefore the EMIF must be
configured to operate in asynchronous mode. As a consequence, the
transfer rate can not be as high as a synchronous rate.

Can someone please help me to clarify it?

Many thanks,

Terry Ranc

(You need to be a member of c6x -- send a blank email to c6x-subscribe@yahoogroups.com )

Terry-

> I have seen a couple of threads mentioning that FIFO can be connected
> to EMIF port in synchronous mode.
> 
> However, from TI application notes it appears that the EMIF does not
> support the synchronous FIFO mode, and therefore the EMIF must be
> configured to operate in asynchronous mode. As a consequence, the
> transfer rate can not be as high as a synchronous rate.
> 
> Can someone please help me to clarify it?

Are you sure that using async EMIF, programmed for no delay between back-to-back
transfers, and combined with DMA transfers to achieve fast consecutive transfers,
maximum data transfer rate is slower than setting up for sync EMIF?  Which TI app
note specifically says that?

-Jeff

(You need to be a member of c6x -- send a blank email to c6x-subscribe@yahoogroups.com )

Thanks Jeff for your reply.

>From the application note "Using TI FIFOs to Interface High-Speed Data Converters with
TI TMS320E DSPs sdma003.pdf", it is stated that because the EMIF does not  support the
synchronous FIFO mode, the EMIF must be configured to operate in asynchronous mode.

And from "TMS320C6000 EMIF to External FIFO Interface spra543.pdf" it takes 5 cycles
to read from the FIFO.

For the application I am working on, the rate of incoming data is about 300 
Mbits/s and the output data rate is about 400 Mbits/s and the DSP is a C62x.The outgoing data
are sent to a FPGA for further processing.
For the incoming data, I am planning to use a FIFO connected either to EMIF and to XBus. For
the outgoing data, ideally the FPGA should be connected to the HPI but it appears it is not
fast enough and I will probably use the XBus.

Regards,

Terry

Jeff Brower <j...@signalogic.com> wrote: Terry-

> I have seen a couple of threads mentioning that FIFO can be connected
> to EMIF port in synchronous mode.
> 
> However, from TI application notes it appears that the EMIF does not
> support the synchronous FIFO mode, and therefore the EMIF must be
> configured to operate in asynchronous mode. As a consequence, the
> transfer rate can not be as high as a synchronous rate.
> 
> Can someone please help me to clarify it?

Are you sure that using async EMIF, programmed for no delay between back-to-back
transfers, and combined with DMA transfers to achieve fast consecutive transfers,
maximum data transfer rate is slower than setting up for sync EMIF?  Which TI app
note specifically says that?

-Jeff

(You need to be a member of c6x -- send a blank email to c6x-subscribe@yahoogroups.com )

Terry-
> From the application note "Using TI FIFOs to Interface High-Speed Data Converters
> with TI TMS320E DSPs sdma003.pdf", it is stated that because the EMIF does not
> support the synchronous FIFO mode, the EMIF must be configured to operate in
> asynchronous mode.
>
> And from "TMS320C6000 EMIF to External FIFO Interface spra543.pdf" it takes 5
> cycles to read from the FIFO.

Is this 5 cycles an "isolated" read by the CPU, or is it back-to-back using a DMA
block?
> For the application I am working on, the rate of incoming data is about 300
> Mbits/s and the output data rate is about 400 Mbits/s and the DSP is a C62x.The
> outgoing data are sent to a FPGA for further processing.
> For the incoming data, I am planning to use a FIFO connected either to EMIF and to
> XBus. For the outgoing data, ideally the FPGA should be connected to the HPI but it
> appears it is not fast enough and I will probably use the XBus.

Ya XBus will work.  I used it in 2001 for DSP-FPGA communication and it's darn fast.
  But that brings up a point -- why are you using a C620x device?  Are you stuck with
a legacy board or something?  It's not going to be that great you can blast data
in/out of the DSP, but you're running code at less than 500 MHz :-(  Plus it's going
to be hard to find online support.  Only people who remember 620x are old-timers like
me and even then it's fuzzy.  In 2006/7, you should be using 641x or by mid-next
year, 6455.  One option on 6415/16 would be UTOPIA.  On 6455 an additional option
would be SRIO.

-Jeff
> Jeff Brower <j...@signalogic.com> wrote:
>
>       Terry-
>
>      > I have seen a couple of threads mentioning that FIFO can be connected
>      > to EMIF port in synchronous mode.
>      >
>      > However, from TI application notes it appears that the EMIF does not
>      > support the synchronous FIFO mode, and therefore the EMIF must be
>      > configured to operate in asynchronous mode. As a consequence, the
>      > transfer rate can not be as high as a synchronous rate.
>      >
>      > Can someone please help me to clarify it?
>
>      Are you sure that using async EMIF, programmed for no delay between
>      back-to-back
>      transfers, and combined with DMA transfers to achieve fast consecutive
>      transfers,
>      maximum data transfer rate is slower than setting up for sync EMIF? Which
>      TI app
>      note specifically says that?
>
>      -Jeff
>

(You need to be a member of c6x -- send a blank email to c6x-subscribe@yahoogroups.com )

Terry,

Off the top of my head <a bit dangerous> - isn't the synchronous FIFO interface almost
the same as SBS RAM?? [sans addresses]  

If  so, I remember that the access speed was 1/2 the CPU clock [the CPU was sub 200 Mhz].

TI had one or more app notes written for the 6201 when it was the 'only family member' [8 years
ago??].  There was also very good documentation on the 6201 EVM that included SBS RAM support. 


mikedunn

----- Original Message ----
From: Jeff Brower <j...@signalogic.com>
To: Terry Ranc <t...@yahoo.co.uk>
Cc: c...@yahoogroups.com
Sent: Friday, November 10, 2006 10:26:39 AM
Subject: Re: [c6x] FIFO to EMIF in synchronous mode

Terry-

> From the application note "Using TI FIFOs to Interface High-Speed Data Converters
> with TI TMS320E DSPs sdma003.pdf" , it is stated that because the EMIF does not
> support the synchronous FIFO mode, the EMIF must be configured to operate in
> asynchronous mode.
>
> And from "TMS320C6000 EMIF to External FIFO Interface spra543.pdf" it takes 5
> cycles to read from the FIFO.

Is this 5 cycles an "isolated" read by the CPU, or is it back-to-back using a DMA
block?

> For the application I am working on, the rate of incoming data is about 300
> Mbits/s and the output data rate is about 400 Mbits/s and the DSP is a C62x.The
> outgoing data are sent to a FPGA for further processing.
> For the incoming data, I am planning to use a FIFO connected either to EMIF and to
> XBus. For the outgoing data, ideally the FPGA should be connected to the HPI but it
> appears it is not fast enough and I will probably use the XBus.

Ya XBus will work. I used it in 2001 for DSP-FPGA communication and it's darn fast.
But that brings up a point -- why are you using a C620x device? Are you stuck with
a legacy board or something? It's not going to be that great you can blast data
in/out of the DSP, but you're running code at less than 500 MHz :-( Plus it's going
to be hard to find online support. Only people who remember 620x are old-timers like
me and even then it's fuzzy. In 2006/7, you should be using 641x or by mid-next
year, 6455. One option on 6415/16 would be UTOPIA. On 6455 an additional option
would be SRIO.

-Jeff

> Jeff Brower <jbrower@signalogic. com> wrote:
>
> Terry-
>
> > I have seen a couple of threads mentioning that FIFO can be connected
> > to EMIF port in synchronous mode.
> >
> > However, from TI application notes it appears that the EMIF does not
> > support the synchronous FIFO mode, and therefore the EMIF must be
> > configured to operate in asynchronous mode. As a consequence, the
> > transfer rate can not be as high as a synchronous rate.
> >
> > Can someone please help me to clarify it?
>
> Are you sure that using async EMIF, programmed for no delay between
> back-to-back
> transfers, and combined with DMA transfers to achieve fast consecutive
> transfers,
> maximum data transfer rate is slower than setting up for sync EMIF? Which
> TI app
> note specifically says that?
>
> -Jeff
>

(You need to be a member of c6x -- send a blank email to c6x-subscribe@yahoogroups.com )

These 5 cycles comes from the interface between the EMIF and the FIFO, and it looks like
it takes also 5 cycles for a back-to-back using DMA.

I first tought of using a C620x or C621x for cost reasons. However, it is true that these
processors may become obsolete so I should probably use C641x as you suggest. Also, as the XBus
is very fast I may connect 2 FIFO, one for the incoming data and one for the outgoing data.

Thanks for your help

Terry

Jeff Brower <j...@signalogic.com> wrote:                                  Terry-
 
 > From the application note "Using TI FIFOs to Interface High-Speed Data Converters
 > with TI TMS320E DSPs sdma003.pdf", it is stated that because the EMIF does not
 > support the synchronous FIFO mode, the EMIF must be configured to operate in
 > asynchronous mode.
 >
 > And from "TMS320C6000 EMIF to External FIFO Interface spra543.pdf" it takes 5
 > cycles to read from the FIFO.
 
 Is this 5 cycles an "isolated" read by the CPU, or is it back-to-back using a DMA
 block?
 
 > For the application I am working on, the rate of incoming data is about 300
 > Mbits/s and the output data rate is about 400 Mbits/s and the DSP is a C62x.The
 > outgoing data are sent to a FPGA for further processing.
 > For the incoming data, I am planning to use a FIFO connected either to EMIF and to
 > XBus. For the outgoing data, ideally the FPGA should be connected to the HPI but it
 > appears it is not fast enough and I will probably use the XBus.
 
 Ya XBus will work.  I used it in 2001 for DSP-FPGA communication and it's darn fast.
   But that brings up a point -- why are you using a C620x device?  Are you stuck with
 a legacy board or something?  It's not going to be that great you can blast data
 in/out of the DSP, but you're running code at less than 500 MHz :-(  Plus it's going
 to be hard to find online support.  Only people who remember 620x are old-timers like
 me and even then it's fuzzy.  In 2006/7, you should be using 641x or by mid-next
 year, 6455.  One option on 6415/16 would be UTOPIA.  On 6455 an additional option
 would be SRIO.
 
 -Jeff
 
 > Jeff Brower <j...@signalogic.com> wrote:
 >
 >       Terry-
 >
 >      > I have seen a couple of threads mentioning that FIFO can be connected
 >      > to EMIF port in synchronous mode.
 >      >
 >      > However, from TI application notes it appears that the EMIF does not
 >      > support the synchronous FIFO mode, and therefore the EMIF must be
 >      > configured to operate in asynchronous mode. As a consequence, the
 >      > transfer rate can not be as high as a synchronous rate.
 >      >
 >      > Can someone please help me to clarify it?
 >
 >      Are you sure that using async EMIF, programmed for no delay between
 >      back-to-back
 >      transfers, and combined with DMA transfers to achieve fast consecutive
 >      transfers,
 >      maximum data transfer rate is slower than setting up for sync EMIF? Which
 >      TI app
 >      note specifically says that?
 >
 >      -Jeff
 >

---------------------------------
 Try the all-new Yahoo! Mail . "The New Version is radically easier to use" – The
Wall Street Journal

(You need to be a member of c6x -- send a blank email to c6x-subscribe@yahoogroups.com )

Terry-
>  These 5 cycles comes from the interface between the EMIF and the FIFO, and it
> looks like it takes also 5 cycles for a back-to-back using DMA.
>
> I first tought of using a C620x or C621x for cost reasons. However, it is true that
> these processors may become obsolete so I should probably use C641x as you suggest.

TI rarely obsoletes a processor, they have an outstanding track record in avoiding
that.  For example you can still purchase C3x and C4x devices that are 12+ years old.
  But they do tend to increase the cost of the older parts, as their way of
"encouraging" customers to move on and upgrade their systems.
> Also, as the XBus is very fast I may connect 2 FIFO, one for the incoming data and
> one for the outgoing data.

Why not look at UTOPIA on C641x?  It has separate Rx and Tx paths, with 400 Mbit/sec
rate in each direction.  At worst it might take a bit of external logic to make it
work with FIFOs.

-Jeff
> Jeff Brower <j...@signalogic.com> wrote:
>
>      Terry-
>
>      > From the application note "Using TI FIFOs to Interface High-Speed Data
>      Converters
>      > with TI TMS320E DSPs sdma003.pdf", it is stated that because the EMIF
>      does not
>      > support the synchronous FIFO mode, the EMIF must be configured to
>      operate in
>      > asynchronous mode.
>      >
>      > And from "TMS320C6000 EMIF to External FIFO Interface spra543.pdf" it
>      takes 5
>      > cycles to read from the FIFO.
>
>      Is this 5 cycles an "isolated" read by the CPU, or is it back-to-back
>      using a DMA
>      block?
>      > For the application I am working on, the rate of incoming data is about
>      300
>      > Mbits/s and the output data rate is about 400 Mbits/s and the DSP is a
>      C62x.The
>      > outgoing data are sent to a FPGA for further processing.
>      > For the incoming data, I am planning to use a FIFO connected either to
>      EMIF and to
>      > XBus. For the outgoing data, ideally the FPGA should be connected to
>      the HPI but it
>      > appears it is not fast enough and I will probably use the XBus.
>
>      Ya XBus will work. I used it in 2001 for DSP-FPGA communication and it's
>      darn fast.
>      But that brings up a point -- why are you using a C620x device? Are you
>      stuck with
>      a legacy board or something? It's not going to be that great you can
>      blast data
>      in/out of the DSP, but you're running code at less than 500 MHz :-( Plus
>      it's going
>      to be hard to find online support. Only people who remember 620x are
>      old-timers like
>      me and even then it's fuzzy. In 2006/7, you should be using 641x or by
>      mid-next
>      year, 6455. One option on 6415/16 would be UTOPIA. On 6455 an additional
>      option
>      would be SRIO.
>
>      -Jeff
>
>      > Jeff Brower <j...@signalogic.com> wrote:
>      >
>      > Terry-
>      >
>      > > I have seen a couple of threads mentioning that FIFO can be connected
>
>      > > to EMIF port in synchronous mode.
>      > >
>      > > However, from TI application notes it appears that the EMIF does not
>      > > support the synchronous FIFO mode, and therefore the EMIF must be
>      > > configured to operate in asynchronous mode. As a consequence, the
>      > > transfer rate can not be as high as a synchronous rate.
>      > >
>      > > Can someone please help me to clarify it?
>      >
>      > Are you sure that using async EMIF, programmed for no delay between
>      > back-to-back
>      > transfers, and combined with DMA transfers to achieve fast consecutive
>      > transfers,
>      > maximum data transfer rate is slower than setting up for sync EMIF?
>      Which
>      > TI app
>      > note specifically says that?
>      >
>      > -Jeff
>

(You need to be a member of c6x -- send a blank email to c6x-subscribe@yahoogroups.com )