Sign in

username:

password:



Not a member?

Search c6x



Search tips

Subscribe to c6x



c6x by Keywords

AD535 | BIOS | Booting | Bootloader | C621 | C6211 | C6415 | C671 | C6711 | C6711DSK | C6713 | CCS | Chassaing | COFF | DAT | DM64 | DM642 | DMA | DSK671 | DSK6711 | EDM | EDMA | EMIF | Emulator | EVM | EVM620 | FFT | FIR | GPIO | Halting | HPI | HWI | IDK | JTAG | LDB | LDH | LDW | Linker | LMS | LOG_printf | Matlab | McBSP | MEM_alloc | MIPS | PCI | PCM3003 | Pipeline | Profiling | QDM | Reset | ROM | RTDX | Sampling | SDRAM | Stack | TEB | THS1206 | TMS320C621 | TMS320C6416 | TMS320C6711 | TMS320C6713 | UART | Vector Table | XBUS | XDS560


Discussion Groups

See Also

Embedded SystemsFPGAElectronics

Discussion Groups | TMS320C6x | Re: HPI problem, Help!!!

Technical discussions about the TI C6000 DSPs (including the c62x, c64x and c67x DSPs).

  

Post a new Thread

Re: HPI problem, Help!!! - Adolf Klemenz - Mar 1 16:56:11 2007

Hi,

   to read from the 6713 HPI you must connect the 6713 HRDY_ output to the 
2407 READY input via an inverter. The 6713 drives HRDY_ high while the HPI 
is busy. This is the only way to make sure data in the HPI is valid. You 
must at least use 1 wait state for the 2407 to accept the READY input.

Also take care to match the HPI timing:
the HPI strobe(s) must be driven low for at least four 6713 CPU clocks, and 
high for at least four cycles between successive accesses.
The four cycles are 13.3ns if the 6713 runs at 300MHz, but if the 6713 
operates at a lower clock (e.g. PLL not yet configured), this timing may be 
significantly longer.

   Best Regards,
   Adolf Klemenz, D.SignT
At 19:11 28.02.2007 +0000, xixidd wrote:

>Hi, I have a problem of 6713 HPI reading. I use 2407evm as the master
>and 6713dsk as the slaver. They are connected by HPI. What I want to do
>is that 2407 writes 10 data to the address starting from 0x80100000 of
>6713 and then reads 4 from the same starting address of 6713. The
>procedure of writting is no peoblem. But the reading is not correct.
>For example, assume that from the address 0x80100000 to 0x8010000C, the
>data are 1,2,3 and 4. Sometimes the data what 2407EVM read from
>0x80100000 to 0x8010000C of 6713DSK is 4,1,2,3. And sometimes the
>second and third data read by 2407EVM are not correct, and always
>changed. If I change the value of the wait state generation register
>WSGR, the performance of HPI reading is also changed. For example, if
>the WSGR is set as 0, meaning no wait state, both the reading and
>writting of HPI are not correct. Who could give some ideas to me? Many
>thanks!
-------------------------------------------------------------------
D.SignT - Digital Signalprocessing Technology GmbH & Co. KG

  Adolf Klemenz

  Gelderner Str.36
  D-47647 Kerken

  phone (+49)(0)2833/570-976
  fax   (+49)(0)2833/3328
  email mailto:a...@dsignt.de
  web   http://www.dsignt.de
-------------------------------------------------------------------

______________________________
Start your Android Ice Cream Sandwich development on TI's AM35x Sitara ARM Cortex-A8 processor today.



(You need to be a member of c6x -- send a blank email to c6x-subscribe@yahoogroups.com )