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Discussion Groups | TMS320C6x | ping pong buffers, QDMA and L1 cache??

Technical discussions about the TI C6000 DSPs (including the c62x, c64x and c67x DSPs).

  

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ping pong buffers, QDMA and L1 cache?? - tino...@yahoo.it - Jun 19 10:26:57 2007

Hi all, 

(...I know there's a lot of posts about cache usage but I'm too much
confused...)

   I have a problem, I want to realize a multichannel implementation of a g729
encoder for c6412.
I DON'T use L2 cache, I use all 256k as internal ram and I want to use external
SDRAM for storing all data of various channels (enc and dec) and I want to use
two buffers in internal ram for faster calculation....
So I want to process a buffer in IRAM while with qdma I'm copyng data for the
next channel to process: I need therefore to transfere from IRAM to SDRAM and
viceversa.
 
Must I invalidate L1 cache before qdma trasfers?? 
Someone can help me? I'm on the right way? 

Thank you
Tino

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