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Discussion Groups | Code-Composer | Problems with XDS510PP Plus and the C6416 TEB from Spectrum Digital

Technical discussions about Code Composer Studio.

  

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Problems with XDS510PP Plus and the C6416 TEB from Spectrum Digital - sapostolacos - Oct 29 11:42:00 2003



I am trying to set up the C6416 TEB from Spectrum Digital on a
Windows 2000 machine. To verify the setup, I am using the SDCONFIG
utility by Spectrum Digital. I have managed (at last) to verify the
connection to the emulator (the product ID is returned to the
utility), but when I am trying to perform JTAG chain test, I receive
a "JTAG DR scan test failed" error. Power to the interface POD and
target hardware is OK, parallel port settings are address setting in
both BIOS and SDCONFIG:0x378, Bios port setting: EPP1..9 and SDCONFIG
port setting: EPP.

Could somebody help me?
Thanks in advance

PS: I have found on the web that there are potential problems with
the JTAG clock line on the board (noise pick-up). Could that be the
problem? Some suggested that a decoupling cap must be used. Does
anybody know anything about the subject?





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RE: Problems with XDS510PP Plus and the C6416 TEB from Spectrum Digital - Sarat Jampani - Oct 30 12:47:00 2003

Hi,

I am also using a C6416TEB & got the same error. However after few
trails, I proceeded further &
the board is working file !!!!. I tested it with the
c:\ti\c6000\teb6416\bin\blink.out file.
NOTE: Even now the error reported is there.
Though I can't explain the reason, I suggest you to proceed further.

Good Luck :-)
Sarat

-----Original Message-----
From: sapostolacos [mailto:]
Sent: Wednesday, October 29, 2003 5:13 PM
To:
Subject: [code-comp] Problems with XDS510PP Plus and the C6416 TEB from
Spectrum Digital I am trying to set up the C6416 TEB from Spectrum Digital on a
Windows 2000 machine. To verify the setup, I am using the SDCONFIG
utility by Spectrum Digital. I have managed (at last) to verify the
connection to the emulator (the product ID is returned to the
utility), but when I am trying to perform JTAG chain test, I receive
a "JTAG DR scan test failed" error. Power to the interface POD and
target hardware is OK, parallel port settings are address setting in
both BIOS and SDCONFIG:0x378, Bios port setting: EPP1..9 and SDCONFIG
port setting: EPP.

Could somebody help me?
Thanks in advance

PS: I have found on the web that there are potential problems with
the JTAG clock line on the board (noise pick-up). Could that be the
problem? Some suggested that a decoupling cap must be used. Does
anybody know anything about the subject?

_____________________________________




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