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For engineers implementing DSP functions on FPGAs. This is a NEW Group that has just been created. It should take a few weeks before the group is big enough to become active. Please join!
Interfacing high speed ADC and DAC to FPGA
amla...@hotmail.com - Apr 27 2010
I have a question regarding high speed A/D converters (> Gsps) and how to interface these to FPGA devices when current FPGA Fmax is in the order of 500MHz.
After some digging a... 
Re:noise of DDC/DUC
Grace - Apr 26 2010
Hi,thanks for reply.Do you mean SFDR of NCO in ddc module? if so ,I have tried to improve it,but it came out the same for output noise.
... Filter basic questions
needtolearnca - Apr 25 2010
Hi,
I'm a logic designer new to the DSP area. I have some basic questions. Any help is appreciated.
I need to design a filter with 5 poles. I read that FIR filters have no po... cic filter and cic compensation filter [2 Articles]
liux...@yahoo.cn - Apr 25 2010
Hello All:
I am designing cic filter and compensation filter. Fs is the signal sample rate and R is the down sample rate with cic filter.I search most of articles about cic+compen... noise of DDC/DUC implemented by CIC and FIR [2 Articles]
grac...@yahoo.com.cn - Apr 25 2010
Hi! can anyone give me some hints on how to handle with the noise of DDC/DUC design implemented by CIC and FIR? I have realized the function of DDC/DUC,but it comes out that the no... quantization and CSD number conversion in FIR filter?
"Yu-Chi T." - Apr 8 2010
Hi everyone, I am reading a paper about FIR filter implementation. However, i have some parts that i am not clear. It proposed a new algorithm for quantization and also use CSD con... vcd file generation with vhdl testbench reading I/o as input
taya...@gmail.com - Mar 29 2010
Hi,
I am working on power analysis of general purpose applications in Quartus-II 9.1. The Model sim was invoked for testbench simulation after compilation of the project in Qua... pre amplifier, adc in spartan 3e kit
mura...@yahoo.co.in - Mar 10 2010
hi friends,
im using spartan 3e kit , and using the preamplifier and adc for analog capture, but when i see the output on chip scope there is a lot of noise...
the input a... xps_adc delta sigma
atlantis2886 - Jan 30 2010
Hello
I am a beginner using FPGA. I make use of EDK. My question is with regards to the xps_deltasigma adc, it is supposed to convert an analog signal to its digital counterpa... Digital Filter (variable sampling rate)
jaso...@gmail.com - Jan 15 2010
Hi. How to design a digital filter that can respond to variable sampling rate?
Any guide or good article on it? Pls recommend.
thanks
...