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For engineers implementing DSP functions on FPGAs. This is a NEW Group that has just been created. It should take a few weeks before the group is big enough to become active. Please join!
4:4:4 to 4:2:2 chroma resampler , filter coefficient
yuga...@yahoo.com - Sep 10 2008
Dear All,
could some through some light on 4:4:4 to 4:2:2 chroma resampler , filter specification foITU r 601, i consult xapp 932.pdf and zip, but my output is not good, so, ple... 
Regarding Input for the pulse shaping filter
srinivas methari - Aug 22 2008
Hi,
Can we apply parallel binary bits to a pulse shaping filter???????
If yes please explain me how to realize that in hardware......
Regards
Methari Srinivas
... Signal communication betweem process in VHDL [2 Articles]
bing...@meidensg.com.sg - Aug 19 2008
Hi,
I found a strange problem. In the following VHDL code, I want to use a signal named (coming) to tell another process data is coming. But I found it did not work.
And if I de... Regarding Interpolation filter
seen...@gmail.com - Aug 7 2008
Hi,
I am implementing Quadrature Amplitude modulator in verilog.
In this first the serial data is converted into parallel form
and applied directly to the pulse shaping filter... Need help with Power estimation for a Xilinx Virtex5 FPGA [2 Articles]
Ishita Dalal - May 1 2008
Hello everyone,I am currently working on a thesis project. As a part of my project, I have developed several design architectures to implement a high speed, memory intensive DSP al... High performance matrix multiplication hardware [2 Articles]
Victor Suarez - Apr 30 2008
Hi.
I need to develop a hardware for hi-performance matrix-to-vector
multiplications.
Say, a hardware that calculates
y = Ax
Being x and y vectors and A a matrix. Vectors ... Simulink DSP Tools [2 Articles]
eyal...@baesystems.com - Apr 27 2008
I'm curious as to what the general attitude of the community towards various Simulink/FPGA DSP tools is.
I am aware of four different existing tools for converting Matlab Simuli... What is the secret of upsampling by 4???
ytac...@ou.edu - Apr 27 2008
Hello,
During my readings in DSP for SDR applications using FPGA, I found an interesting note which is the upsampling ratio of 4. I found this in two different locations, one at... 256MB/S data rate interface with FPGA
tian...@163.com - Apr 20 2008
Hi everyone,
I am evaluating a wireless receiver solution,
cound you give me some advise?
the bandwidth of signal is about 64Mhz,
if choose 4x smapling rate, which center fr... IIR filter in VHDL [3 Articles]
"kamran.wadood" - Apr 1 2008
Hi there,
I am implementing an IIR filter in VHDL/FPGA. I've done it in
MATLAB/SIMULINK as a starting point in 2 ways:
1. using FDA tool
2. using cannonic diagram (putting in ...