Hello. I am building an FPGA based software radio.
It has a direct sampling ADC that then interfaces with the FPGA.
My ADC has a 50 mhz bandwidth, and I would like to selectively choose ~1 mhz
to send to the computer for further processing.

I would like to have 5 different "channels" (5 different segments)  be
able
to be sent to the computer.
I would like 200khz bandwidth at: 28mhz, 21mhz, 14mhz, 7mhz, and 3.5mhz.

How I am currently trying to this is:
ADC input -> FPGA
Inside the FPGA:
A DDS generates 5 phase signals that are incremented at the 5 frequencies.
Those phase signals are sent to 5 CORDIC rotators that are set up like this:
ADC in -> X in; 0 -> Y in; phase -> phase in
(this is equivalent to using a complex multiplier.)
The output of the CORDIC rotator is an I Q representation of the frequency
shifted input signal.
this is then filtered to 200khz bandwidth
and then sent to a second CORDIC rotator (with a second DDS) to be shifted
enough to "stack" 5 segments of spectrum into one contiguous signal.

ADC -> FIFO stack -> Multiplexor -> CORDIC->I   -> CIC filter
-> FIR filter
-> CORDIC -> I
..................................................................->Q ->
CIC
filter -> FIR filter -> CORDIC ------->Q
..................................................-> CORDIC->I   ->
CIC
filter -> FIR filter -> CORDIC->+I
..................................................................->Q ->
CIC
filter -> FIR filter -> CORDIC------->+Q
..................................................-> CORDIC->I   ->
CIC
filter -> FIR filter -> CORDIC->+I
..................................................................->Q ->
CIC
filter -> FIR filter -> CORDIC------->+Q
..................................................-> CORDIC->I   ->
CIC
filter -> FIR filter -> CORDIC->+I
..................................................................->Q ->
CIC
filter -> FIR filter -> CORDIC------->+Q
..................................................-> CORDIC->I   ->
CIC
filter -> FIR filter -> CORDIC->+I
..................................................................->Q ->
CIC
filter -> FIR filter -> CORDIC------->+Q

and then the Summed I and Q signals are sent to a microcontroller, and then
the microcontroller sends the signals to a PC over ethernet.

Is there a more efficient way to "stack" these signals?

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