Hi all,

I am working on FPGA Implementation of fixed-point FFT and trying to minimize
resources.

I have 4 parallel samples coming from ADC into FPGA. I want to calculate
1024-point FFT of the input stream. To do this, I have 4 FFT's of 256-point
running in parallel. I am planning on multiplying the input stream with
necessary twiddle factors before I send it to the 4 FFT's running in parallel.

My main questions is that:

1) Xilinx FFT Cores expose real an imaginary input for each of the FFT.
Since my input stream is real, instead of tying the imaginary component to zero,
I want to use it. I want to compute Real FFT using Complex FFT Cores provided by
Xilinx. By doing so, I can reduce the required parallel FFT's from 4 to 2 (50%
reduction in FPGA resources). This is similar to App Note described by TI:
http://processors.wiki.ti.com/index.php/Efficient_FFT_Computation_of_Real_Input

2) If I configure the FFT Core as Fixed-Point, Unscaled Output. Can I feed two
real inputs to Real, Imaginary part of Xilinx Core and later perform math to get
real FFT. I read somewhere if the Core is configured as Single-Precision FFT,
there won't be rounding issues. With Fixed-Point, Unscaled Output, will be there
be any rounding issues?

Any thoughts/ suggestions are greatly appreciated. Feel free to post any
questions if I am not clear.

rakumarudu

______________________________
New Code Sharing Section now Live on DSPRelated.com. Learn about the Reward Program for Contributors here.



(You need to be a member of fpgadsp -- send a blank email to fpgadsp-subscribe@yahoogroups.com )