Hi there,
I am implementing an IIR filter in VHDL/FPGA. I've done it in 
MATLAB/SIMULINK as a starting point in 2 ways:
1. using FDA tool
2. using cannonic diagram (putting in coefficient values)

Now, am trying to implement this number 2. implementing the cannonic 
diagram in VHDL which has got some delay elements and the 
multiplication/addition of these elements together with filter 
coefficients. I want to know that:
a) How to put in a sinusoidal input in VHDL?
b) How to represent these values of coefficients like 1.09, -0.38 
etc. in VHDL?
c) multiplication and addition of these coefficients with the input 
and its delayed versions?
d) How to put in the delay?

I am working on it myself but any feedback (even on any of these 
bits) or any suggestions e.g. some useful links etc. will be 
appreciated. 

I will be really grateful if any of you guys out there could suggest 
a different method or some additional things that could be done in 
order to implement an IIR filter in VHDL/FPGA, for some one who's 
quite keen to develop the skills in DSP and FPGA field.

Thanks in advance,
Kamran

Dear Kamran:
 
A really quick way to design the IIR filter in VHDL would be to use the
'filterbuilder' tool in matlab.
In addition, Mathworks offers a "Filter Design HDL Coder" license which
is pretty nice for quickly generating synthesizable RTL.
When installed, a tab on the 'filterbuilder' UI says 'code generation'
and there are plenty of options there to generate the filter and
testbench code.
The testbench setups are what you would expect for a filter - for
example, impulse response and step response, among others.
 
(a) Being a newbie myself and before getting the "Filter Design HDL
Coder", I generated signals in simulink, and wrote them to a text file,
read them in with my (verilog) simulator, and read the vectors from my
simulator back into matlab for frequency analysis --> there are probably
better ways to do this.
 
(d) a delay is modeled as a register, the register's internal clock to q
delay is based on timing models for your target logic circuits.
 
Best Regards,
Russell

________________________________

	From: f...@yahoogroups.com [mailto:f...@yahoogroups.com]
On Behalf Of kamran.wadood
	Sent: Sunday, March 30, 2008 7:33 PM
	To: f...@yahoogroups.com
	Subject: [fpgadsp] IIR filter in VHDL

	Hi there,
	I am implementing an IIR filter in VHDL/FPGA. I've done it in 
	MATLAB/SIMULINK as a starting point in 2 ways:
	1. using FDA tool
	2. using cannonic diagram (putting in coefficient values)
	
	Now, am trying to implement this number 2. implementing the
cannonic 
	diagram in VHDL which has got some delay elements and the 
	multiplication/addition of these elements together with filter 
	coefficients. I want to know that:
	a) How to put in a sinusoidal input in VHDL?
	b) How to represent these values of coefficients like 1.09,
-0.38 
	etc. in VHDL?
	c) multiplication and addition of these coefficients with the
input 
	and its delayed versions?
	d) How to put in the delay?
	
	I am working on it myself but any feedback (even on any of these

	bits) or any suggestions e.g. some useful links etc. will be 
	appreciated. 
	
	I will be really grateful if any of you guys out there could
suggest 
	a different method or some additional things that could be done
in 
	order to implement an IIR filter in VHDL/FPGA, for some one
who's 
	quite keen to develop the skills in DSP and FPGA field.
	
	Thanks in advance,
	Kamran

Hello,

a)  If the sinusoidal input is for a test bench, the general way is to read a a set of test
vectors that correspond to a sinusoidal input.  If you're trying to implement a sine wave in
VHDL, you will need a lookup table to do it.

b)  For the coefficients, you will need a fixed point library.  I would recommend, in general
for FPGA DSP design, to use one of the many Matlab/Simulink -> HDL tools - It makes this
sort of design a lot less cumbersome.  Keep in mind that for the coefficients you will likely
need at least 16 bits (if not more!) depending on the rate your filter runs at.

c)  Addition will likely be handled by whichever fixed point library you use.  Multiplication
can be more difficult, and may require you to instantiate a specific hardware component in your
VHDL (ie an embedded multiplier in a Spartan 3).  

d)  Delays are flipflops.  You can implement a simple D register to create a one cycle delay.

My experiences with IIR filters in FPGAs is that they require wide bit paths to avoid numerical
errors.  I've had filter paths as wide as 32 bits, which can get expensive in an FPGA with
coefficient multiplication.  

Good luck,
Eyal

Hi there,
>I am implementing an IIR filter in VHDL/FPGA. I've done it in 
>MATLAB/SIMULINK as a starting point in 2 ways:
>1. using FDA tool
>2. using cannonic diagram (putting in coefficient values)
>
>Now, am trying to implement this number 2. implementing the cannonic 
>diagram in VHDL which has got some delay elements and the 
>multiplication/addition of these elements together with filter 
>coefficients. I want to know that:
>a) How to put in a sinusoidal input in VHDL?
>b) How to represent these values of coefficients like 1.09, -0.38 
>etc. in VHDL?
>c) multiplication and addition of these coefficients with the input 
>and its delayed versions?
>d) How to put in the delay?
>
>I am working on it myself but any feedback (even on any of these 
>bits) or any suggestions e.g. some useful links etc. will be 
>appreciated. 
>
>I will be really grateful if any of you guys out there could suggest 
>a different method or some additional things that could be done in 
>order to implement an IIR filter in VHDL/FPGA, for some one who's 
>quite keen to develop the skills in DSP and FPGA field.
>
>Thanks in advance,
>Kamran
>