For engineers implementing DSP functions on FPGAs. This is a NEW Group that has just been created. It should take a few weeks before the group is big enough to become active. Please join!
Hi, I'm developing my own custom hardware design of FFT algorithm (radix-2, CORDIC based), the design is resources constrained, with certain timing requirements to be met (timing constraints are relaxed). Now, I want to evaluate my design versus other area optimized reference designs. I searched in Altera reference designs library, but the FFT design there is balanced between time and area optimization, however what I'm looking for is a purely resources optimized design to have fair evaluation of my design. Anybody can help? Thanks in advance.______________________________