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Discussion Groups | DSP & FPGA | FIR Filter Implementation in Verilog HDL

For engineers implementing DSP functions on FPGAs. This is a NEW Group that has just been created. It should take a few weeks before the group is big enough to become active. Please join!

  

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FIR Filter Implementation in Verilog HDL - engi...@yahoo.com - Dec 3 7:53:51 2008

1) I need a simple to code in Verilog HDL for implementing a FIR Filter.
Filter equation is as under :
y[n] = 1/3(x[n] + x [n-1] + x[n-2]

2) Is there any book availaible for implementing DSPs in Verilog HDL..

Thanks




Re: FIR Filter Implementation in Verilog HDL - tom....@gmail.com - Oct 22 8:19:38 2009

The easiest (although maybe not the most efficient) way to implement this
filter would be something like:

/** Verilog code */
module fir (
  input signed [SAMPLE_WIDTH] new_sample,  //incoming sample
  input clk,                               //sample clock
  output reg signed [SAMPLE_WIDTH] y);     //filtered output

  //use signed registers to perform signed arithmetic

always @ (posedge clk) begin

   y <= (x_n + x_nm1 + x_nm2) / 3;  //y[n]
   x_nm2 <= x_nm1;                  //x[n-2]
   x_nm1 <= x_n;                    //x[n-1]
   x_n <= new_sample;               //x[n]

end

endmodule
/** End of Verilog code */

The biggest problem with this code is that it uses a divide.  As you probably
know, division is very slow and expensive in hardware, and so you're much better
off trying to massage your filter coefficients into powers of two in order to be
able to perform division using a bit shift (shifting left by n corresponds to
multiplication by 2^n, shifting right by n corresponds to division by 2^n).  If
you're working with a large filter with many taps, and can't make them all into
powers of 2, you might be better off using a system clock that runs (much)
faster than the sample clock, and sharing one multiplier between all filter
taps.  

For information on Verilog DSP work, I suggest you start by looking at some of
the design examples given at
http://www.altera.com/support/examples/dsp/exm-dsp.html.

Hope this helps.
--Tom
1) I need a simple to code in Verilog HDL for implementing a FIR Filter.
>Filter equation is as under :
>y[n] = 1/3(x[n] + x [n-1] + x[n-2]
>
>2) Is there any book availaible for implementing DSPs in Verilog HDL..
>
>Thanks
>





RE: Re: FIR Filter Implementation in Verilog HDL - John Miles - Oct 26 21:37:16 2009

> 1) I need a simple to code in Verilog HDL for implementing a FIR Filter.
> >Filter equation is as under :
> >y[n] = 1/3(x[n] + x [n-1] + x[n-2]
> >
> >2) Is there any book availaible for implementing DSPs in Verilog HDL..

There's some Verilog code in Uwe Meyer-Baese's book on DSP with FPGAs.  (I
have this book but haven't actually tried to use it yet, so can't give it a
thumbs-up or thumbs down.)

-- john, KE5FX




Re: FIR Filter Implementation in Verilog HDL - cfel...@ieee.org - Oct 27 12:06:16 2009


1) I need a simple to code in Verilog HDL for implementing a FIR Filter.
>Filter equation is as under :
>y[n] = 1/3(x[n] + x [n-1] + x[n-2]

The difference equation that was posted is simply a moving average.  Couple
things, look at the filter requirements (cutoff freq, position nulls, etc).  If
you change the order of the moving average to 4 you will not need the divide. 
There are resource efficient algorithms for moving average.  A recursive
structure (similar to a  CIC filter) only requires adders.  

I would also suggest using something like MyHDL (www.myhdl.org) to design,
implement, and simulate any DSP HDL.  It is much easier to integrate signal
processing simulation with the HDL simulation.  Makes analyzing and verifying
DSP blocks much easier.

>
>2) Is there any book availaible for implementing DSPs in Verilog HDL..
>
The  Uwe Meyer-Baese book is decent.  As previously mentioned it has Verilog and
VHDL examples.  A general DSP book like Lyons' "Understanding Digital
Signal Processing" would also be a good book.  Couple other VSLI DSP books
out there as well, Parhi and Wanhammar.  The later books are a more in depth but
good.  I don't think the Parhi has HDL (Verilog/VHDL) examples but the others
do.