For engineers implementing DSP functions on FPGAs. This is a NEW Group that has just been created. It should take a few weeks before the group is big enough to become active. Please join!
I am making an AM transmitter and receiver on SFF SDR Development Platform. I am using model based approach. I have completed my Upssmpoling model using System Generator , Now what i understand is to multiply the message signal with some carrier and then upconvert it and translate it to some IF and send it to DAC and RF module.These are the problems 1. When i multiply my message signal with a carrier ,i get a lots of images ,and the filter to remove those has to be very sharp 2. How can i translate my message signal to some higher frequency before doing upsampling 3. What should be the frequency of my message signal , i am having a 4KHz signal 4. I need to implement it on the kit using only the FPGA part P.S: The ADC and DAC are 125 MS/s and 200 MS/s. Kindly do help :(______________________________