For engineers implementing DSP functions on FPGAs. This is a NEW Group that has just been created. It should take a few weeks before the group is big enough to become active. Please join!
hi, I'm puzzled that is there method implementing the pin-to-pin connection in FPGA or CPLD.it means there is no buffer on the route. It act as a wire that connets two pins on FPGA or CPLD.______________________________