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Discussion Groups | DSP & FPGA | Interfacing high speed ADC and DAC to FPGA

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Interfacing high speed ADC and DAC to FPGA - amla...@hotmail.com - Apr 27 7:54:10 2010

I have a question regarding high speed A/D converters (> Gsps) and how
to interface these to FPGA devices when current FPGA Fmax is in the order of
500MHz.

After some digging around Iâve seen a suggestion of using the a SERDES
primitive, on for example the ADC interface, which can be configured to split
the high speed ADC bus into a number of concurrent buses running at a fraction
of the ADC clock. This would provide a feasible means for getting >Gsps
sample data into the device, but leaves the complication of how to manage
multiple concurrent buses for a single sample stream.

I wondered, is this the way DSP/FPGA community achieve this, or are there other
techniques out there?

Kind regards

Adrian 

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