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Discussion Groups

Discussion Groups | Freescale DSPs | DSP56303EVM and PLL configuration

Technical discussions about Freescale (Motorola) DSPs (including the DSP56000, DSP56300, DSP56600, 56800 DSPs).

  

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DSP56303EVM and PLL configuration - GuillaumeDesj - May 23 17:15:00 2003



Hi,

I am currently trying to get my DSP56303EVM board to run at a
frequency close to 100Mhz. According to the documentation,
Fextal=12.288Mhz. I have therefore configured the PCTL register with
the following value: $50007

This enables PLL operation and sets the XTLD bit. The MF bits take
the value of 7. The output clock should therefore be

12.288*(7+1) = 98... Mhz

I originally thought this was working well since the frequency
counter gave me the correct value. When i tried analyzing CLKOUT
using a logic analyzer however, i noticed that the clock was
experiencing some little technical difficulties, the duty cycle and
clock period varying dramatically from one pulse to the other.

Has anyone ever had this problem ?

I obviously looked in the motorola documentation and noticed
somewhere that it says skew elimination is only guaranteed for MF <=
4. Would this explain my problem or am i just doing something wrong ?

Thanks in advance.
Guillaume





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Re: DSP56303EVM and PLL configuration - Christian Langen - May 24 7:28:00 2003

Currently I am using

movep #$050006,X:M_PCTL ; DSP core at 12.288x7 = 86.016MHz

in one of my apps running the DSP56364. Maybe the missing leading zero in
your value makes the difference.... Please take a look what is stored in your
pctl register. I guess $500070 which makes no sense...

regards

Christian

> Hi,
>
> I am currently trying to get my DSP56303EVM board to run at a
> frequency close to 100Mhz. According to the documentation,
> Fextal=12.288Mhz. I have therefore configured the PCTL register with
> the following value: $50007
>
> This enables PLL operation and sets the XTLD bit. The MF bits take
> the value of 7. The output clock should therefore be
>
> 12.288*(7+1) = 98... Mhz
>
> I originally thought this was working well since the frequency
> counter gave me the correct value. When i tried analyzing CLKOUT
> using a logic analyzer however, i noticed that the clock was
> experiencing some little technical difficulties, the duty cycle and
> clock period varying dramatically from one pulse to the other.
>
> Has anyone ever had this problem ?
>
> I obviously looked in the motorola documentation and noticed
> somewhere that it says skew elimination is only guaranteed for MF <=
> 4. Would this explain my problem or am i just doing something wrong ?
>
> Thanks in advance.
> Guillaume >
> _____________________________________
> /groups.php3
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