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Discussion Groups | Freescale DSPs | Can't get SPI to work

Technical discussions about Freescale (Motorola) DSPs (including the DSP56000, DSP56300, DSP56600, 56800 DSPs).

  

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Can't get SPI to work - mvl818 - Oct 21 13:15:00 2003

Hi,

I'm trying to use the DAC on a 56F805 EVB and
can't even get the SPI to work.
I put an oscilloscope on spclk and then mosi and
don't even get a single pulse.

Here is some of the code I've tried:

#define PEPUR 0x0FF0 /* GPIOE_BASE 0x0FF0 */
#define PEDR 0x0FF1
#define PEDDR 0x0FF2
#define PEPER 0x0FF3
#define PEIAR 0x0FF4
#define PEIENR 0x0FF5
#define PEIPOLR 0x0FF6
#define PEIPR 0x0FF7
#define PEIESR 0x0FF8

/* SPI registers set up for MAXIM 5251 DAC on 56F805 EVB */
#define SPSCR 0x0F20 /* SPI_BASE 0x0F20 */
#define SPDSR 0x0F21 /* data size reg. */
#define SPDRR 0x0F22
#define SPDTR 0x0F23
#define SPI_CONTROL_WORD 0x015C
#define SPI_DATA_SIZE 0x000F
#define SPI_ADDR_CTRL_FLAG 0x3000 /* 0011 load dac1 */
#define SPTE_FLAG 0x0200 /* transmitter empty flag */
#define SPRF_FLAG 0x2000 /* receive full flag */ *SPDSR = SPI_DATA_SIZE; /* set up SPI to MAX5251 DAC on evb */
*SPSCR = SPI_CONTROL_WORD; /* 0x015C */
*PEPER |= 0x0070;/* GPIOE4-6 to SPI peripheral */
*PEPER &= ~0x0080;/* GPIOE7 will serve as /SS so reset PEPER bit 7 */
*PEDDR |= 0x0080; /* it is output */
*PEDR &= 0x0080;/* SS is active low so set it since dsp is master */

*SPSCR |= 0x0002; /* set SPI enable bit */

while (1) { /* loop forever */

if( *SPSCR & SPTE_FLAG )
{
*SPIDTR = 0xF0F0; /* send something to spi */
}
delay(for_a_while);
}

Can anyone tell me what I'm doing wrong?
Is there somewhere else where I have to enable the SPI output?

Thanks,

Mike




_____________________________
 Free pdf download: Complex Digital Signal Processing in Telecommunications.




RE: Can't get SPI to work - Corey, Rick - Oct 21 13:51:00 2003

Hi Mike

You don't have to set SS yourself - once you "assign" that pin to the SPI
peripheral, it will set it for you. Your Control word ($015C) seems to
enable MODFEN, so you had better be catching any interrupts caused by
overruns or naughty SS behavior ... but maybe with CPHA=1, there can be no
naughty SS behavior. I would disable MODFEN until after I got something
working. Maybe you need to set the PER registers *before* configuring the
SCR. Are you sure your DAC doesn't need SS?

I never got my 56803 working with CPHA=1 ... I saw SCLK and data, but the
data bit-shifted like a pig on ice.

I just saw a new errata sheet for the 805, with new SPI errata, oh joy!
(DSP56F805E -
http://e-www.motorola.com/files/dsp/doc/errata/DSP56F805E.pdf
- if you don't find it on the Moto site, I'll forward a copy on request)

I still don't have SPI working well or reliably as a Slave with interrupts,
but I've heard it is better behaved as Master, and polled. Here's a snippet
that at least generates pulses on an 803 ... your addresses may vary. I use
9-bit data. If you see pulses but still get garbage data, Try adding long
delays between each word - like 30 microseconds. I was able to add a 2-uSec
delay between asserting SS and the first SCLK transition because I'm using a
ColdFire QSPI as Master.

I think that setting the data direction register is unnecessary, but I did
it out of paranoia.

I've gotten zero assistance from Digital DNA and DSPO on using SPI as a
Slave ... I think they tried but no one answered to say whether they had the
same problem, couldn't recreate it, or asking for more info. Several people
offered to help, or to send it to "their best person", but the most
substantive reply I've gotten was an anonymous one-liner "check the errata".

I heard the rumor that some SPI silicon errata were fixed in "another DSP
family", but Moto has not reved the 803 to include these fixes - if so, I
would think the same problems must exist in the 805. The same rumor source
suggested that not many people would use a DSP as Slave, so we would rely on
Motorola's testing. I've mostly heard of people using 568xx chips' SPI in
Master, polled mode, not Slave, interrupts.

I don't know about the 805, but we bought five 803 evaluation boards with
grossly old, flawed silicon, including one "Proto A" rev chip and one
"Pilsen B" rev. Out of five boards, we didn't get even one Rev F chip - and
the sales rep basically said "that's too bad". If you are using a Motorola
eval board, check the date code and errata sheet very carefully - total
non-function as a result of Moto selling you useless silicon revs is quite
possible, I'm sad to say. // ********* setup 4 GPIO_E pins to be used by SPI: MOSI, MISO, SCLK &
/SS E4, E5, E6 & E7
// ********* set DDR (data direction) also, unnecessarily
*********************************
periphBitSet( 0x00F0, (unsigned short *)(GPIO_E_PER) ); // 4 GPIO
pins: peripheral enable
periphBitSet( 0x0040, (unsigned short *)(GPIO_E_DDR) ); // set bit
#6 (MISO is OUTPUT, GPIOE6)
periphBitClear( 0x00B0, (unsigned short *)(GPIO_E_DDR) ); // clear
bits 4-5--7, inputs

// ********* SPI Data Size Register
************************************
*(unsigned short *)(SPDSR) = 0x0008 ; // SPI Data Size Register==8
means word size of 9 bits

// ********* SPI Status and Control Register Section 13.9.1 DSP80x User
Manual
*(unsigned short *)(SPSCR) = 0x0028 ; // $28=SPRIE & CPOL only
(CPHA=0, Slave, no MODFEN)

// ********* now write a code word to TxDataRegister to tell ColdFire
that DSP0 "woke up"
*(unsigned short *)(SPDTR) = SPI_DSP0_READY ; // I doubt if this is
needed by anyone but me

// ********* ENable SPI: SCR |= $0002
***********************************
periphBitSet( SPI_ENABLE_BIT_SPE, (unsigned short *)(SPSCR) ); //
enable SPI peripheral

Please let me know if you get it working!

Rick Corey

-----Original Message-----
From: mvl818 [mailto:]
Sent: Tuesday, October 21, 2003 9:16 AM
To:
Subject: [motoroladsp] Can't get SPI to work Hi,

I'm trying to use the DAC on a 56F805 EVB and
can't even get the SPI to work.
I put an oscilloscope on spclk and then mosi and
don't even get a single pulse.

Here is some of the code I've tried:

#define PEPUR 0x0FF0 /* GPIOE_BASE 0x0FF0 */
#define PEDR 0x0FF1
#define PEDDR 0x0FF2
#define PEPER 0x0FF3
#define PEIAR 0x0FF4
#define PEIENR 0x0FF5
#define PEIPOLR 0x0FF6
#define PEIPR 0x0FF7
#define PEIESR 0x0FF8

/* SPI registers set up for MAXIM 5251 DAC on 56F805 EVB */
#define SPSCR 0x0F20 /* SPI_BASE 0x0F20 */
#define SPDSR 0x0F21 /* data size reg. */
#define SPDRR 0x0F22
#define SPDTR 0x0F23
#define SPI_CONTROL_WORD 0x015C
#define SPI_DATA_SIZE 0x000F
#define SPI_ADDR_CTRL_FLAG 0x3000 /* 0011 load dac1 */
#define SPTE_FLAG 0x0200 /* transmitter empty flag */
#define SPRF_FLAG 0x2000 /* receive full flag */ *SPDSR = SPI_DATA_SIZE; /* set up SPI to MAX5251 DAC on evb */
*SPSCR = SPI_CONTROL_WORD; /* 0x015C */
*PEPER |= 0x0070;/* GPIOE4-6 to SPI peripheral */
*PEPER &= ~0x0080;/* GPIOE7 will serve as /SS so reset PEPER bit 7 */
*PEDDR |= 0x0080; /* it is output */
*PEDR &= 0x0080;/* SS is active low so set it since dsp is master */

*SPSCR |= 0x0002; /* set SPI enable bit */

while (1) { /*
loop forever */

if( *SPSCR & SPTE_FLAG )
{
*SPIDTR = 0xF0F0; /* send something to spi */
}
delay(for_a_while);
}

Can anyone tell me what I'm doing wrong?
Is there somewhere else where I have to enable the SPI output?

Thanks,

Mike

_____________________________________
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_____________________________
 Free pdf download: Complex Digital Signal Processing in Telecommunications.