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Discussion Groups | Freescale DSPs | 56F803: Access to external Interface hangs the CAN-Interface

Technical discussions about Freescale (Motorola) DSPs (including the DSP56000, DSP56300, DSP56600, 56800 DSPs).

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56F803: Access to external Interface hangs the CAN-Interface - thomaskracke - Dec 14 17:17:00 2003

Hallo DSP'lers, I'm working with the 56F803. I connected a FPGA (APEX form Altera) to the external memory-interface. I decode the lines A0-A7, WR\, RD\, PS\ and DS\. I address the FPGA in the Address-Range from 0x2000..0x20ff. It works fine, I can read and write every FPGA-register. But: After a time of about two minutes the CAN-Receiver of the 56F803 stops working. There is no error-flag set in the MSCAN-registers (CANRFLAG, CANRXERR, CANTXERR) and if I look with the debugger into the CAN-registers after it stopped working everything seems to be fine: 0x0df80: CAN_CTL0 = 0x00D0 (SYNC, RXACT, RXFRM) 0x0df81: CAN_CTL1 = 0x0080 (CANE = CAN is enabled, ext. Clock) 0x0df82: CAN_BTR0 = 0x0001 \ 500bK, 75% 0x0df83: CAN_BTR1 = 0x0014 / 0x0df84: CAN_RFLG = 0x0000 no error, no message 0x0df85: CAN_RIER = 0x0000 no interrupts enable, I poll CAN 0x0df86: CAN_TFLG = 0x0007 no message transmitting right now 0x0df87: CAN_TCR = 0x0000 I do not use this features 0x0df88: CAN_IDAC = 0x0010 Four 16-Bit Identifiers 0x0df8E: CAN_RXERR= 0x0000 no errors visible here 0x0df8F: CAN_TXERR= 0x0000 no errors visible here I read CAN_RXERR and CAN_TXERR with MSCAN in softreset, too, but they contain really no errors. The interesting thing is, that bit RXACT in CAN_CTL0 is set the hole time. Maybe the CAN-Controller hangs inside. But why can read accesses to external memory makes the can controller hanging? Where is the connection? I checked out for shorts, the power-supply and crosstalk. But CAN-lines are far away from the memory interface of the DSP and really have no connection with the external interface. If I only make write accesses to the FPGA everything is fine. If I make any read accesses, the effect comes after a few minutes. If I make accesses to the external interface, where no physical memory or registers are, everything is fine. I checked the access-timing of the FPGA, too. It looks ok, 5ns after the RD\ went high the data-lines between FPGA and DSP are floating. I'm working with 4 waitstates. Did anybody had similar effects? Any ideas? I worked on this problem a few days (and nights) and I'm a little bit desperated. Thomas

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RE: 56F803: Access to external Interface hangs the CAN-Interface - Hutchings William-p23437 - Dec 15 16:44:00 2003

The first thing I would try is to clock the MSCAN module from the internal clock source and not the external clock source. Please see the FAQ on the subject for more details. While it is not clear why your external memory interfaces would be causing undo clock noise I would do a test.

My version of the DSP56F80X Users manual recommends that the EXTAL clock be used for the MSCAN clock source. But I wish to use the IP bus clock to get greater flexibility in the rates I can clock CAN bus. I have also found that using the IP bus clock seems to be more reliable in noisy environments. Can I use IPbus clock as the source for the MSCAN module?

Last Modified date

22APR2003

Problem Categories

Question. My version of the DSP56F80X Users manual recommends that the EXTAL clock be used for the MSCAN clock source. But I wish to use the IP bus clock to get greater flexibility in the rates I can clock CAN bus. I have also found that using the IP bus clock seems to be more reliable in noisy environments. Can I use IPbus clock as the source for the MSCAN module?

Answer. The answer is yes you can choose the IPbus clock as the clock source for the MSCAN module by setting the CLKSRC bit in the CANCTL1 register to a one. In fact since the time the manuals were printed we have further tested both the IPbus and the EXTAL_CLK clocking modes of the MSCAN peripheral and found that the IPbus is superior and is now the recommended choice.

The IPbus exhibits less clock jitter than the EXTAL_CLK and it has also been found to have greater noise immunity than the EXTAL_CLK source in very noisy environments or board designs. Hence choosing the IPbus clock mode makes for more reliable CAN communications. In addition choosing the IPbus clock mode enables CAN bus transfer rates of greater than 500Kbits/sec. The EXTAL_CLK mode can be used if desired and will meet the CAN bus jitter requirements, but is no longer the recommended source for the MSCAN module clock.

-----Original Message-----
From: thomaskracke [mailto:t...@yahoo.com]
Sent: Sunday, December 14, 2003 10:17 AM
To: m...@yahoogroups.com
Subject: [motoroladsp] 56F803: Access to external Interface hangs the CAN-Interface

Hallo DSP'lers, I'm working with the 56F803. I connected a FPGA (APEX form Altera) to the external memory-interface. I decode the lines A0-A7, WR\, RD\, PS\ and DS\. I address the FPGA in the Address-Range from 0x2000..0x20ff. It works fine, I can read and write every FPGA-register. But: After a time of about two minutes the CAN-Receiver of the 56F803 stops working. There is no error-flag set in the MSCAN-registers (CANRFLAG, CANRXERR, CANTXERR) and if I look with the debugger into the CAN-registers after it stopped working everything seems to be fine: 0x0df80: CAN_CTL0 = 0x00D0 (SYNC, RXACT, RXFRM) 0x0df81: CAN_CTL1 = 0x0080 (CANE = CAN is enabled, ext. Clock) 0x0df82: CAN_BTR0 = 0x0001 \ 500bK, 75% 0x0df83: CAN_BTR1 = 0x0014 / 0x0df84: CAN_RFLG = 0x0000 no error, no message 0x0df85: CAN_RIER = 0x0000 no interrupts enable, I poll CAN 0x0df86: CAN_TFLG = 0x0007 no message transmitting right now 0x0df87: CAN_TCR = 0x0000 I do not use this features 0x0df88: CAN_IDAC = 0x0010 Four 16-Bit Identifiers 0x0df8E: CAN_RXERR= 0x0000 no errors visible here 0x0df8F: CAN_TXERR= 0x0000 no errors visible here I read CAN_RXERR and CAN_TXERR with MSCAN in softreset, too, but they contain really no errors. The interesting thing is, that bit RXACT in CAN_CTL0 is set the hole time. Maybe the CAN-Controller hangs inside. But why can read accesses to external memory makes the can controller hanging? Where is the connection? I checked out for shorts, the power-supply and crosstalk. But CAN-lines are far away from the memory interface of the DSP and really have no connection with the external interface. If I only make write accesses to the FPGA everything is fine. If I make any read accesses, the effect comes after a few minutes. If I make accesses to the external interface, where no physical memory or registers are, everything is fine. I checked the access-timing of the FPGA, too. It looks ok, 5ns after the RD\ went high the data-lines between FPGA and DSP are floating. I'm working with 4 waitstates. Did anybody had similar effects? Any ideas? I worked on this problem a few days (and nights) and I'm a little bit desperated. Thomas

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