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Discussion Groups | Freescale DSPs | IRQA interrupt flag on 56F803

Technical discussions about Freescale (Motorola) DSPs (including the DSP56000, DSP56300, DSP56600, 56800 DSPs).

  

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IRQA interrupt flag on 56F803 - rootesracer - Dec 31 0:32:00 2003

I have a unique hardware problem that I am trying to resolve in
software.

The problem is that under some conditions, I am getting an edge
triggered interrupt on IRQA, that sometimes because of a logic
glitch, I get a second edge 100ns or so later, which causes me
to execute the interrupt twice. I would like to know if it is somehow possible to detect from within
the ISR that another interrupt for IRQA is pending, and to cancel it
prior to exiting the ISR.

I read the F80X family manual on the interrupt details, and it is
rather lacking in info. Any help would be appreciated.




_____________________________
 Free pdf download: Complex Digital Signal Processing in Telecommunications.




Re: IRQA interrupt flag on 56F803 - Charlie W - Jan 5 16:19:00 2004

Most time this happened due to signal bounce. If a
mechanical switch is used to generate interrupt
signal, a debouncing circuit is necessary. The simple
debouncing circuit is Flip-Flop.

Charlie
--- rootesracer <> wrote:
> I have a unique hardware problem that I am trying to
> resolve in
> software.
>
> The problem is that under some conditions, I am
> getting an edge
> triggered interrupt on IRQA, that sometimes because
> of a logic
> glitch, I get a second edge 100ns or so later, which
> causes me
> to execute the interrupt twice. > I would like to know if it is somehow possible to
> detect from within
> the ISR that another interrupt for IRQA is pending,
> and to cancel it
> prior to exiting the ISR.
>
> I read the F80X family manual on the interrupt
> details, and it is
> rather lacking in info. > Any help would be appreciated.

__________________________________




_____________________________
 Free pdf download: Digital Signal Processor Fundamentals and System Design.




Re: IRQA interrupt flag on 56F803 - Mariano Filippa - Jan 5 20:56:00 2004

Why don't you try masking IRQA for a definite period of time when asserted?
In the ISR of IRQA, write to IPR to mask further IRQA interrupts, then you
could use a timer to enable it after a certain ammount of time. I'm not sure
if this could work...

MPF

----- Original Message -----
From: "Charlie W" <>
To: "rootesracer" <>;
<>
Sent: Monday, January 05, 2004 11:19 AM
Subject: Re: [motoroladsp] IRQA interrupt flag on 56F803 > Most time this happened due to signal bounce. If a
> mechanical switch is used to generate interrupt
> signal, a debouncing circuit is necessary. The simple
> debouncing circuit is Flip-Flop.
>
> Charlie
> --- rootesracer <> wrote:
> > I have a unique hardware problem that I am trying to
> > resolve in
> > software.
> >
> > The problem is that under some conditions, I am
> > getting an edge
> > triggered interrupt on IRQA, that sometimes because
> > of a logic
> > glitch, I get a second edge 100ns or so later, which
> > causes me
> > to execute the interrupt twice.
> >
> >
> > I would like to know if it is somehow possible to
> > detect from within
> > the ISR that another interrupt for IRQA is pending,
> > and to cancel it
> > prior to exiting the ISR.
> >
> > I read the F80X family manual on the interrupt
> > details, and it is
> > rather lacking in info.
> >
> >
> > Any help would be appreciated.
> >
> >
> >
> >
> > __________________________________
>
> _____________________________________
> /groups.php3



_____________________________
 Free pdf download: Digital Signal Processor Fundamentals and System Design.




Re: IRQA interrupt flag on 56F803 - Mariano Filippa - Jan 5 21:06:00 2004

Checking DSP56800 family manual: page 7-6

"...The execution of the JSR instruction stacks the PC and the SR as it
transfers control to the first instruction in the interrupt service routine.
These two stacked registers contain the 16-bit return address that will
later be used to return to the interrupted code, as well as the condition
code state. In addition, the IPL is raised to level 1 to disallow any level
0 interrupts. Note that the OnCE trap, stack error, illegal instruction, and
SWI can still generate interrupts because these are level 1 interrupts and
are non-maskable..."

RTI restores the SR and enables again the interrupts. What you can do to
avoid this is to access the stored SR in the stack and modify the I1 bit to
mask further interrupts. Then enable it back with a timer.

I'm not sure if you can get the same effect just by writing to IPR (IAL1 and
IAL0) to mask IRQA interrupts. This would be convinient since you don't have
to modify the SR in the stack. Then enable it back with a timer.

MPF ----- Original Message -----
From: "Mariano Filippa" <>
To: <>
Sent: Monday, January 05, 2004 3:56 PM
Subject: Re: [motoroladsp] IRQA interrupt flag on 56F803 > Why don't you try masking IRQA for a definite period of time when
asserted?
> In the ISR of IRQA, write to IPR to mask further IRQA interrupts, then you
> could use a timer to enable it after a certain ammount of time. I'm not
sure
> if this could work...
>
> MPF
>
> ----- Original Message -----
> From: "Charlie W" <>
> To: "rootesracer" <>;
> <>
> Sent: Monday, January 05, 2004 11:19 AM
> Subject: Re: [motoroladsp] IRQA interrupt flag on 56F803 > > Most time this happened due to signal bounce. If a
> > mechanical switch is used to generate interrupt
> > signal, a debouncing circuit is necessary. The simple
> > debouncing circuit is Flip-Flop.
> >
> > Charlie
> > --- rootesracer <> wrote:
> > > I have a unique hardware problem that I am trying to
> > > resolve in
> > > software.
> > >
> > > The problem is that under some conditions, I am
> > > getting an edge
> > > triggered interrupt on IRQA, that sometimes because
> > > of a logic
> > > glitch, I get a second edge 100ns or so later, which
> > > causes me
> > > to execute the interrupt twice.
> > >
> > >
> > > I would like to know if it is somehow possible to
> > > detect from within
> > > the ISR that another interrupt for IRQA is pending,
> > > and to cancel it
> > > prior to exiting the ISR.
> > >
> > > I read the F80X family manual on the interrupt
> > > details, and it is
> > > rather lacking in info.
> > >
> > >
> > > Any help would be appreciated.
> > >
> > >
> > >
> > >
> > >
> >
> >
> > __________________________________
> >
> > _____________________________________
> > /groups.php3
> >
> >
> >
> >
> >
> >
>



_____________________________
 Free pdf download: Digital Signal Processor Fundamentals and System Design.




RE: IRQA interrupt flag on 56F803 - Corey, Rick - Jan 5 21:50:00 2004

Hi Mariano

As I read the Family Manual (7-13 through 7-16 in the 1996 paper edition),
that should be all you have to do to mask IRQA. Poke the IPR at $FFFB.
Page 7-16 distinguishes between edge-sensitive and level-sensitive behavior.

The IPR enables or disables each channel 0..6, and seems to promise the same
for IRQA and B. I would expect that to be sufficient to block IRQA.

(Disclaimer: I've never browsed the errata sheet for IRQA/B quirks.)

Rick Corey -----Original Message-----
From: Mariano Filippa [mailto:]
Sent: Monday, January 05, 2004 4:06 PM
To:
Subject: Re: [motoroladsp] IRQA interrupt flag on 56F803 Checking DSP56800 family manual: page 7-6

"...The execution of the JSR instruction stacks the PC and the SR as it
transfers control to the first instruction in the interrupt service routine.
These two stacked registers contain the 16-bit return address that will
later be used to return to the interrupted code, as well as the condition
code state. In addition, the IPL is raised to level 1 to disallow any level
0 interrupts. Note that the OnCE trap, stack error, illegal instruction, and
SWI can still generate interrupts because these are level 1 interrupts and
are non-maskable..."

RTI restores the SR and enables again the interrupts. What you can do to
avoid this is to access the stored SR in the stack and modify the I1 bit to
mask further interrupts. Then enable it back with a timer.

I'm not sure if you can get the same effect just by writing to IPR (IAL1 and
IAL0) to mask IRQA interrupts. This would be convinient since you don't have
to modify the SR in the stack. Then enable it back with a timer.

MPF ----- Original Message -----
From: "Mariano Filippa" <>
To: <>
Sent: Monday, January 05, 2004 3:56 PM
Subject: Re: [motoroladsp] IRQA interrupt flag on 56F803 > Why don't you try masking IRQA for a definite period of time when
asserted?
> In the ISR of IRQA, write to IPR to mask further IRQA interrupts, then you
> could use a timer to enable it after a certain ammount of time. I'm not
sure
> if this could work...
>
> MPF
>
> ----- Original Message -----
> From: "Charlie W" <>
> To: "rootesracer" <>;
> <>
> Sent: Monday, January 05, 2004 11:19 AM
> Subject: Re: [motoroladsp] IRQA interrupt flag on 56F803 > > Most time this happened due to signal bounce. If a
> > mechanical switch is used to generate interrupt
> > signal, a debouncing circuit is necessary. The simple
> > debouncing circuit is Flip-Flop.
> >
> > Charlie
> > --- rootesracer <> wrote:
> > > I have a unique hardware problem that I am trying to
> > > resolve in
> > > software.
> > >
> > > The problem is that under some conditions, I am
> > > getting an edge
> > > triggered interrupt on IRQA, that sometimes because
> > > of a logic
> > > glitch, I get a second edge 100ns or so later, which
> > > causes me
> > > to execute the interrupt twice.
> > >
> > >
> > > I would like to know if it is somehow possible to
> > > detect from within
> > > the ISR that another interrupt for IRQA is pending,
> > > and to cancel it
> > > prior to exiting the ISR.
> > >
> > > I read the F80X family manual on the interrupt
> > > details, and it is
> > > rather lacking in info.
> > >
> > >
> > > Any help would be appreciated.
> > >
> > >
> > >
> > >
> > >
> >
> >
> > __________________________________
> >
> > _____________________________________
> > /groups.php3
> >
> >
> >
> >
> >
> >
>
_____________________________________
/groups.php3




_____________________________
 Free pdf download: Digital Signal Processor Fundamentals and System Design.