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Hi, iam simply confused. i did read the datasheets and have understood the following. from the datasheet ,and from the register ADCR2 which gives u the clock divisor frequency N= clock dividor select value =DIV +1 FADC = FIPR/(2N) FIPR = 40MHz/2 = 20MHz DIV N FADC 0011 (default start)4 5MHz 0100 5 4MHz . . . 1100 12 1.66MHz . 1111 16(dec) 1.25MHz ADLST1 and 2 REGISTERS only choose the respective channels to be used ADSDIS Register enables the respective sample in a ADLST1 -2 and from what i read ,i have understood that adc takes 8.5clock cycles to do 1 sample conversion,and an addition of 6 clock cycles for the next sample conversion. but then what is the minimum sampling rate that can be set? and what r the sampling rates that 56805 adc can take? iam getting confused with the adc clock and the samping rate. can anyone shed some light on this pls. thanx in advance. Bye, kubra

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