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Discussion Groups

Discussion Groups | Freescale DSPs | unknown memory locations?

Technical discussions about Freescale (Motorola) DSPs (including the DSP56000, DSP56300, DSP56600, 56800 DSPs).

  

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unknown memory locations? - joemccarr - Sep 5 16:10:00 2002



I am going trough the FSTART.C code
To understand what it takes to set up the
Processor for a C program. FSTART.C <snippit>
#define TCR01 0xFFDF
#define TCR2 0xFFDA
#define MCR2 0XFFD2
#define SPCR0 0xFFE2
#define SPCR1 0xFFE6
<end snippit)

I can not find any documentation on what registers reside
Between X:$FFC1 and X:$FFF8

Can anyone steer me to some docs explaining
This part of memory.

I am using the 56805

Thanks
Joe McCarron





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RE: unknown memory locations? - Art Johnson - Sep 5 18:59:00 2002

Look in the following SDK file:
...\src\dsp56805evm\nos\include\arch.h
The "..." is whichever directory you installed the SDK under, in my
system it's:
C:\Development\DSP568xx\Moto_SDK

The memory from 0xFF80 to 0xFFFF is in the arch_sCore structure as
follows:

typedef volatile struct{
UWord16 Reserved1[0x79];
UWord16 BusControlReg;
UWord16 Reserved2;
UWord16 InterruptPriorityReg;
UWord16 Reserved3[3];
UWord16 BusTransferReg;
} arch_sCore;

The location of the ArchCore structure is defined in the "linker.cmd"
file as follows:
.xCoreRegisters (RW) : ORIGIN = 0xFF80, LENGTH = 0x0080
FArchCore = ADDR(.xCoreRegisters);

This address is defined to be the DSP chip Core registers at the end of
the "arch.h" file:
/* The locations of the following structures are defined in linker.cmd
*/
EXPORT arch_sIO ArchIO;
EXPORT arch_sCore ArchCore;

I hope this helps.

Regards,

Art Johnson
Senior Systems Analyst
PMC Prime Mover Controls Inc.
3600 Gilmore Way
Burnaby, B.C., Canada
V5G 4R8
Phone: 604 433-4644
FAX: 604 433-5570
Email:
http://www.pmc-controls.com
-----Original Message-----
From: joemccarr [mailto:]
Sent: Thursday, September 05, 2002 9:10 AM
To:
Subject: [motoroladsp] unknown memory locations? I am going trough the FSTART.C code
To understand what it takes to set up the
Processor for a C program. FSTART.C <snippit>
#define TCR01 0xFFDF
#define TCR2 0xFFDA
#define MCR2 0XFFD2
#define SPCR0 0xFFE2
#define SPCR1 0xFFE6
<end snippit)

I can not find any documentation on what registers reside
Between X:$FFC1 and X:$FFF8

Can anyone steer me to some docs explaining
This part of memory.

I am using the 56805

Thanks
Joe McCarron
_____________________________________
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