Development of a Block Floating Point Interval ALU for DSP and Control Applications
By Sandeep Krishnanand Hattangady
With the advent of interval arithmetic, numerical analysis on real numbers has come to be classified into theoretical analysis or analysis based on point-wise arithmetic, and interval analysis or analysis based on interval arithmetic. With computational reliability gaining importance, interval analysis has been proposed as a technique to provide a certificate of reliability to the computations. However, software implementations for interval arithmetic show poor execution rates. Therefore, computationally intense applications in digital signal processing and control systems resort to fixed-point hardware implementations, which provide better solutions to these problems with high throughput. However, fixed point architectures are susceptible to overflow errors leading to unreliable results, which cannot be tolerated with interval operations in particular. This work develops a Block Floating Point Interval ALU (BFPIALU) to attain reliable interval arithmetic on fixed point architectures. BFP support is provided through the ability to perform special BFP operations such as Exponent Detection and Normalization in its command set. Overflow is handled by a need-based scaling technique known as Conditional Block Floating Point Scaling (CBFS) technique. The ability to perform point-wise computations is also included by incorporating modifications in the interval architecture that allow it to function as two parallel ALU units for such computations. This work presents a four-stage pipelined architecture is presented that performs upto 258.4 million interval operations per second. The architecture can also perform 516.8 million point-wise operations per second.
Download Document(This item is protected by original copyright)
Rate this document: