A Two-Level Reconfigurable Cell Array for Digital Signal Processing
By Mitchell Johnm Myjak
Reconfigurable hardware has become an attractive option for implementing digital signal
processing, especially in systems that require both high performance and flexibility. This
thesis presents a novel two-level reconfigurable architecture targeted toward systems with
these requirements. The architecture supports a large orthogonal design space whereby
designers can customize the word length, amount of parallelism, number of functional units,
and functional unit connectivity to meet the needs of the application.
On the upper level, algorithms are mapped onto an array of 4-bit cells and a hierarchical
interconnection fabric. The interconnection structure contains a mesh of 4-bit busses for local
data transfer, as well as an H-tree for communicating results between functional units. On
the lower level, each cell contains a small matrix of elements that collectively implement all
necessary operations. The matrix of elements has only two configurations: one optimized for
mathematical functions such as multiply-accumulates, and the other optimized for memory
operations. The system also contains pipeline latches to maximize clock rate and throughput.
Circuit simulations indicate that the architecture achieves a clock frequency of 200 MHz
in a modest 0.25-μm CMOS technology. An initial prototype of the reconfigurable cell has
been fabricated in 0.5-μm CMOS and tested for functionality. The estimated execution
time for a 16-bit, 256-point Fast Fourier Transform shows a speedup ranging from 1.6 to 14
compared to contemporary digital signal processors.
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