ES Week Emphasis on Component Based Design

Posted by Praveen Raghavan on Oct 7 2007 under Academia / Research | Design Methodolgies   

Howdy everyone from beautiful Salzburg/Austria,

A week full of presentations on embedded systems at ESWeek was quite a mindful. Similar to most academic conferences, there was only a few papers worth taking back home to think about. Amongst these were:

1. Keynote talk by Hermann Eul from Infineon: He presented Infineon's view on SDR and its evolution. This talk was quite inspirational. However the most interesting slide on complexity of SDR evolution was removed. I wish I could give this information.

2. Keynote talk by Jane W.S. Liu from SISAL: She presented a very different view on electronics and its evolution. She presented a view where the design is human-centric instead of machine-centric as it is now. My personal view on this is that we do need to take into account humans, but the design itself need tot always be human-centric.

3. In general over different technical discussion, the stress for a programming model, automation for MPSoC platforms is very important. This was concurred from the EMSoft Panel Discussion on grand challenges in embedded systems to special sessions at CASES and CODES to various keynotes.

4. Keynote by Chris Rowen/Tensilica: Chris gave a very interesting talk on Tensilica's work on instruction set extension. Once again consistent with the rest of industry's trend, Tensilica also seems to be moving towards automation of putting together MPSoCs. Besides Tensilica's XRES compiler for generating a single processor with efficient ILP, DLP and complex functional units, their focus has started to shift towards MPSoC systems where many processors can be put together using direct connections, buses, queues, and other standard interfaces.

5.VLIW processor from Toshiba: Toshiba revealed its VCP processor (Vector CoProcessor). The target domain for VCP is is front end image/video processing algorithms like Edge detection, histogram calculation, adaptive prefilter etc. The VCP is a 6 way VLIW, 3 vector slots, 6 scalar slots. They seem to have some special instruction encoding to enable looping. However they do not have a compiler in place yet. Given the complexity of micro-architecture, the compiler is not going to be easy at all. They claim to be working on the compiler framework for this. This architecture seems similar to IMEC's Syncpro , developed by yours truly!

Besides the above industrial views on things, I shall also try to make a list of relatively good academic papers in the next post.

Cheers

 

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posted by Praveen Raghavan
Praveen is a PhD researcher at IMEC vzw in Belgium. He is also a PhD candidate at KULeuven in Electrical Engineering, Belgium. He works in the area of digital signal processor design for low power Software Defined Radio. He received his master in Electrical Engineering from Arizona State University, USA and before which he received his Bachelors in Electrical Engineering from REC, Trichy, India. Praveen's interests include processor design, compilers for DSP, low power, system design. | Personal website

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