Processor: Not Relevant
Submitted by Christopher Felton on Aug 23 2011
Licensed under a Creative Commons Attribution 3.0 Unported License
This code snippet illustrates how to use the SIIR object to genrate Verilog and VHDL for a Direct Form I IIR Lowpass filter. More information available from this blog post and code for the SIIR object is available here.
To use the generator download and install the dependencies, download the Python script, and either modify the script (bottom, main script execution) or execute the commands in the code snippet section.
* siir object (above link)
* python 2.7 (tested with 2.7)
* numpy (numpy.scipy.org)
* scipy (www.scipy.org)
* MyHDL (www.myhdl.org)
Example Plots Generated; the designed filter response.
The simulated filter response.
After running the Convert method the Verilog and VHDL will be generated. The Verilog or VHDL can then be used in normal FPGA process.