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Hi People, I'm trying to think of an efficient way to implement a Shaped OQPSK modulator in hardware (FPGA or CPLD). My first thought was to use an FIR filter. However, since there are only two input bits per symbol, there are only a relatively small number of output states and (it seems) a LUT could be much more efficient. Has anyone thought through this a little better and have any pointers or suggestions? -- Randy Yates % "And all you had to say Digital Signal Labs % was that you were mailto://y...@ieee.org % gonna stay." http://www.digitalsignallabs.com % Getting To The Point', *Balance of Power*, ELO

On 3/27/2010 6:36 PM, Randy Yates wrote: > Hi People, > > I'm trying to think of an efficient way to implement a Shaped OQPSK > modulator in hardware (FPGA or CPLD). My first thought was to use an FIR > filter. However, since there are only two input bits per symbol, there > are only a relatively small number of output states and (it seems) a LUT > could be much more efficient. > > Has anyone thought through this a little better and have any pointers > or suggestions? A lut is a very common way to implement a modulator. You only need enough address bits to cover N symbols plus however many phases you want per symbol (four is often enough). You can even add address bits for different pulse shapes or modulation orders. Even in an FPGA, if the symbol rate is fixed, this is often the most efficient way to do it. -- Eric Jacobsen Minister of Algorithms Abineau Communications http://www.abineau.com

Randy Yates <y...@ieee.org> wrote: > I'm trying to think of an efficient way to implement a Shaped OQPSK > modulator in hardware (FPGA or CPLD). My first thought was to use an FIR > filter. However, since there are only two input bits per symbol, there > are only a relatively small number of output states and (it seems) a LUT > could be much more efficient. Well, the primary logic unit of an FPGA is look-up table. If you are multiplying by constants, especially with a two bit input, yes, look-up tables are likely the best way. It is usual for FPGAs to have flip-flops at the output of each LUT, which makes systolic array pipelines real easy to build. If you latch at each logic level, they are really fast, too! Not knowing OQPSK, can you describe a little what expression you need evaluated? -- glen

Randy Yates wrote: > Hi People, > > I'm trying to think of an efficient way to implement a Shaped OQPSK > modulator in hardware (FPGA or CPLD). My first thought was to use an FIR > filter. However, since there are only two input bits per symbol, there > are only a relatively small number of output states and (it seems) a LUT > could be much more efficient. > > Has anyone thought through this a little better and have any pointers > or suggestions? Using LUT for modulators is pretty common; see G3RUH GMSK modem for example. However, FPGA utilization is going to be rather inefficient if you need LUT for more then, say, 256 entries. I cheer those who work on weekends. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com

On Sun, 28 Mar 2010 06:59:26 -0500, Vladimir Vassilevsky <n...@nowhere.com> wrote: >I cheer those who work on weekends. What's a weekend? Greg

>Randy Yates <y...@ieee.org> wrote: > >> I'm trying to think of an efficient way to implement a Shaped OQPSK >> modulator in hardware (FPGA or CPLD). My first thought was to use an FIR >> filter. However, since there are only two input bits per symbol, there >> are only a relatively small number of output states and (it seems) a LUT >> could be much more efficient. > >Well, the primary logic unit of an FPGA is look-up table. > >If you are multiplying by constants, especially with a two bit >input, yes, look-up tables are likely the best way. > >It is usual for FPGAs to have flip-flops at the output of each >LUT, which makes systolic array pipelines real easy to build. >If you latch at each logic level, they are really fast, too! > >Not knowing OQPSK, can you describe a little what expression >you need evaluated? > >-- glen QAM shaping by root raised cosine is commonly done in a multiplierless transposed FIR structure using precomputed products(LUTs). If you are also upsampling by 2(least practical requirement)then you can split up the structure to two polyphases. The LUTs need to be as many as the number of longest polyphase taps with each LUT of a small size suitable for your levels.The symbol bit pattern can then be used to address all LUTs and get the products in the serial chain of adders. By far this is the most efficient structure than using multipliers. It also suits several QAM modes and you change the LUTs readily for rolloff or gain control...etc. kaz >

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Greg Berchin wrote:
> On Sun, 28 Mar 2010 06:59:26 -0500, Vladimir Vassilevsky <n...@nowhere.com>
> wrote:
>
>
>>I cheer those who work on weekends.
>
>
> What's a weekend?
A periodical thing when the other folks are trying to distract you from
work.
VLV
```

Eric Jacobsen <e...@ieee.org> writes: > On 3/27/2010 6:36 PM, Randy Yates wrote: >> Hi People, >> >> I'm trying to think of an efficient way to implement a Shaped OQPSK >> modulator in hardware (FPGA or CPLD). My first thought was to use an FIR >> filter. However, since there are only two input bits per symbol, there >> are only a relatively small number of output states and (it seems) a LUT >> could be much more efficient. >> >> Has anyone thought through this a little better and have any pointers >> or suggestions? > > A lut is a very common way to implement a modulator. You only need > enough address bits to cover N symbols plus however many phases you > want per symbol (four is often enough). You can even add address bits > for different pulse shapes or modulation orders. > > Even in an FPGA, if the symbol rate is fixed, this is often the most > efficient way to do it. Right. The basic thing I was wrapping my brain around was the completely different viewpoint of an FIR as a finite state machine (a Mealy FSM, to be precise). I'd never thought of it that way. For a K-bit input, there are 2^(K*N) states where N is the FIR length. Therefore a LUT with K*N address inputs and L output bits suffices to describe the filter. When K and N are big (say, K = 16 and N = 32), it's impractical to use a LUT. But for small values it becomes feasible; maybe even preferable... OK, I think I'm now sufficiently out of the rut of "everything is a MAC"... -- Randy Yates % "Bird, on the wing, Digital Signal Labs % goes floating by mailto://y...@ieee.org % but there's a teardrop in his eye..." http://www.digitalsignallabs.com % 'One Summer Dream', *Face The Music*, ELO

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e precise). I'd never thought of it that way.
>
>For a K-bit input, there are 2^(K*N) states where N is the FIR length.
>Therefore a LUT with K*N address inputs and L output bits suffices to
>describe the filter.
>
>When K and N are big (say, K = 16 and N = 32), it's impractical to use a
>LUT. But for small values it becomes feasible; maybe even preferable...
>
>OK, I think I'm now sufficiently out of the rut of "everything is a
>MAC"...
>--
Is there any math / theorems that describe the behavior of a FIR filter as
a state-machine (trellis?). Could there exist a direct relation between,
say the state variable (2**(K*N)), and the output? If there was a direct
relationship between the state-variable and the output a large
state-variable and corresponding state-machine might be reasonable resource
usage.
I think from this perspective a traditional FIR maintains multiple state
information and computes the output?
chris
```

glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: >It is usual for FPGAs to have flip-flops at the output of each >LUT, which makes systolic array pipelines real easy to build. >If you latch at each logic level, they are really fast, too! Doesn't the usual definition of "systolic array" require that there is no globally synchrnous clock, that instead the clock follows the data around? And if so, would one really design with an FPGA in such a fashion? Steve