I am designing  filter to do decimation at the output of a Sigma Delta
modulator. Here is the spec -

Sampling frequency - Fs - 1.4MHz
Decimation factor - D - 100
Input - 3 bits
Output resolution - 13 bits.

The filter, and the modulator are reset every 100 clock cycles.

I tried using a CIC filter, but since it is to be reset every 100 clock
cycles, I am limited to order 1. I will not get 13 bit resolution with 1
order.

I am looking at two stage filter now. The questions are

1. Will a 2 stage CIC work? First stage - Order 5, with decimation 20,
Second stage - Order 4 with decimation 5, or something similar

2. Any pointers to two stage decimation filter design are appreciated.

The important point is that the filter is to be reset every 100 clock
cycles.

On 06/29/2010 09:03 AM, analog_fever wrote:
> I am designing  filter to do decimation at the output of a Sigma Delta
> modulator. Here is the spec -
>
> Sampling frequency - Fs - 1.4MHz
> Decimation factor - D - 100
> Input - 3 bits
> Output resolution - 13 bits.
>
> The filter, and the modulator are reset every 100 clock cycles.
>
> I tried using a CIC filter, but since it is to be reset every 100 clock
> cycles, I am limited to order 1. I will not get 13 bit resolution with 1
> order.
>
> I am looking at two stage filter now. The questions are
>
> 1. Will a 2 stage CIC work? First stage - Order 5, with decimation 20,
> Second stage - Order 4 with decimation 5, or something similar
>
> 2. Any pointers to two stage decimation filter design are appreciated.
>
> The important point is that the filter is to be reset every 100 clock
> cycles.
>
>
Why must it be reset after 100 clock cycles?

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html

>On 06/29/2010 09:03 AM, analog_fever wrote:
>> I am designing  filter to do decimation at the output of a Sigma Delta
>> modulator. Here is the spec -
>>
>> Sampling frequency - Fs - 1.4MHz
>> Decimation factor - D - 100
>> Input - 3 bits
>> Output resolution - 13 bits.
>>
>> The filter, and the modulator are reset every 100 clock cycles.
>>
>> I tried using a CIC filter, but since it is to be reset every 100 clock
>> cycles, I am limited to order 1. I will not get 13 bit resolution with
1
>> order.
>>
>> I am looking at two stage filter now. The questions are
>>
>> 1. Will a 2 stage CIC work? First stage - Order 5, with decimation 20,
>> Second stage - Order 4 with decimation 5, or something similar
>>
>> 2. Any pointers to two stage decimation filter design are appreciated.
>>
>> The important point is that the filter is to be reset every 100 clock
>> cycles.
>>
>>
>Why must it be reset after 100 clock cycles?
>
>-- 
>
>Tim Wescott
>Wescott Design Services
>http://www.wescottdesign.com
>
>Do you need to implement control loops in software?
>"Applied Control Theory for Embedded Systems" was written for you.
>See details at http://www.wescottdesign.com/actfes/actfes.html
>

That is a requirement from the modulator design. It, and the filter is to
be reset at the start of each ADC conversion.

On 6/29/2010 12:38 PM, analog_fever wrote:
>> On 06/29/2010 09:03 AM, analog_fever wrote:
>>> I am designing  filter to do decimation at the output of a Sigma Delta
>>> modulator. Here is the spec -
>>>
>>> Sampling frequency - Fs - 1.4MHz
>>> Decimation factor - D - 100
>>> Input - 3 bits
>>> Output resolution - 13 bits.
>>>
>>> The filter, and the modulator are reset every 100 clock cycles.
>>>
>>> I tried using a CIC filter, but since it is to be reset every 100 clock
>>> cycles, I am limited to order 1. I will not get 13 bit resolution with
> 1
>>> order.
>>>
>>> I am looking at two stage filter now. The questions are
>>>
>>> 1. Will a 2 stage CIC work? First stage - Order 5, with decimation 20,
>>> Second stage - Order 4 with decimation 5, or something similar
>>>
>>> 2. Any pointers to two stage decimation filter design are appreciated.
>>>
>>> The important point is that the filter is to be reset every 100 clock
>>> cycles.
>>>
>>>
>> Why must it be reset after 100 clock cycles?
>>
>> --
>>
>> Tim Wescott
>> Wescott Design Services
>> http://www.wescottdesign.com
>>
>> Do you need to implement control loops in software?
>> "Applied Control Theory for Embedded Systems" was written for you.
>> See details at http://www.wescottdesign.com/actfes/actfes.html
>>
>
> That is a requirement from the modulator design. It, and the filter is to
> be reset at the start of each ADC conversion.

Filters have startup transients. How are repeated transients handled?

Jerry
-- 
Engineering is the art of making what you want from things you can get.
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯

>On 6/29/2010 12:38 PM, analog_fever wrote:
>>> On 06/29/2010 09:03 AM, analog_fever wrote:
>>>> I am designing  filter to do decimation at the output of a Sigma
Delta
>>>> modulator. Here is the spec -
>>>>
>>>> Sampling frequency - Fs - 1.4MHz
>>>> Decimation factor - D - 100
>>>> Input - 3 bits
>>>> Output resolution - 13 bits.
>>>>
>>>> The filter, and the modulator are reset every 100 clock cycles.
>>>>
>>>> I tried using a CIC filter, but since it is to be reset every 100
clock
>>>> cycles, I am limited to order 1. I will not get 13 bit resolution
with
>> 1
>>>> order.
>>>>
>>>> I am looking at two stage filter now. The questions are
>>>>
>>>> 1. Will a 2 stage CIC work? First stage - Order 5, with decimation
20,
>>>> Second stage - Order 4 with decimation 5, or something similar
>>>>
>>>> 2. Any pointers to two stage decimation filter design are
appreciated.
>>>>
>>>> The important point is that the filter is to be reset every 100 clock
>>>> cycles.
>>>>
>>>>
>>> Why must it be reset after 100 clock cycles?
>>>
>>> --
>>>
>>> Tim Wescott
>>> Wescott Design Services
>>> http://www.wescottdesign.com
>>>
>>> Do you need to implement control loops in software?
>>> "Applied Control Theory for Embedded Systems" was written for you.
>>> See details at http://www.wescottdesign.com/actfes/actfes.html
>>>
>>
>> That is a requirement from the modulator design. It, and the filter is
to
>> be reset at the start of each ADC conversion.
>
>Filters have startup transients. How are repeated transients handled?
>
>Jerry
>-- 
>Engineering is the art of making what you want from things you can get.
>������������������������������ï¿
½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿
½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½
>

Have not really thought about what you mentioned.

analog_fever wrote:
>> On 6/29/2010 12:38 PM, analog_fever wrote:
>>>> On 06/29/2010 09:03 AM, analog_fever wrote:
>>>>> I am designing  filter to do decimation at the output of a Sigma
> Delta
>>>>> modulator. Here is the spec -
>>>>>
>>>>> Sampling frequency - Fs - 1.4MHz
>>>>> Decimation factor - D - 100
>>>>> Input - 3 bits
>>>>> Output resolution - 13 bits.
>>>>>
>>>>> The filter, and the modulator are reset every 100 clock cycles.
>>>>>
>>>>> I tried using a CIC filter, but since it is to be reset every 100
> clock
>>>>> cycles, I am limited to order 1. I will not get 13 bit resolution
> with
>>> 1
>>>>> order.
>>>>>
>>>>> I am looking at two stage filter now. The questions are
>>>>>
>>>>> 1. Will a 2 stage CIC work? First stage - Order 5, with decimation
> 20,
>>>>> Second stage - Order 4 with decimation 5, or something similar
>>>>>
>>>>> 2. Any pointers to two stage decimation filter design are
> appreciated.
>>>>> The important point is that the filter is to be reset every 100 clock
>>>>> cycles.
>>>>>

It appears to me that this is a matter of physics perhaps not supporting 
the objective.  Well, if I have the numbers right:

Sample at 1.4MHz.
Decimate by a factor of 100.
Sample for 100 "clock" cycles.
Does that mean 71.4usec (100 samples at 1.4MHz)?
or
Does that mean 7.14msec (100 samples at 14kHz) after decimation?

If the former, the best transition band width you can get is roughly 
14kHz.  And, that happens to be the sample rate after decimation.  So, 
that can't work no matter the transient which is another problem as 
Jerry points out.

If the latter, the best transition band width you can get is roughly 
140Hz.  So that makes more sense.  And, if you figure you might only 
need 20% of half-band transistion that would be 20% of 7kHz or 1.4kHz.
Then the transient (and effective filter unit sample length) might be 10 
samples and a real system could be built to do this.

I'm still unclear about the "reset" though ....  ??

Fred

>analog_fever wrote:
>>> On 6/29/2010 12:38 PM, analog_fever wrote:
>>>>> On 06/29/2010 09:03 AM, analog_fever wrote:
>>>>>> I am designing  filter to do decimation at the output of a Sigma
>> Delta
>>>>>> modulator. Here is the spec -
>>>>>>
>>>>>> Sampling frequency - Fs - 1.4MHz
>>>>>> Decimation factor - D - 100
>>>>>> Input - 3 bits
>>>>>> Output resolution - 13 bits.
>>>>>>
>>>>>> The filter, and the modulator are reset every 100 clock cycles.
>>>>>>
>>>>>> I tried using a CIC filter, but since it is to be reset every 100
>> clock
>>>>>> cycles, I am limited to order 1. I will not get 13 bit resolution
>> with
>>>> 1
>>>>>> order.
>>>>>>
>>>>>> I am looking at two stage filter now. The questions are
>>>>>>
>>>>>> 1. Will a 2 stage CIC work? First stage - Order 5, with decimation
>> 20,
>>>>>> Second stage - Order 4 with decimation 5, or something similar
>>>>>>
>>>>>> 2. Any pointers to two stage decimation filter design are
>> appreciated.
>>>>>> The important point is that the filter is to be reset every 100
clock
>>>>>> cycles.
>>>>>>
>
>It appears to me that this is a matter of physics perhaps not supporting 
>the objective.  Well, if I have the numbers right:
>
>Sample at 1.4MHz.
>Decimate by a factor of 100.
>Sample for 100 "clock" cycles.
>Does that mean 71.4usec (100 samples at 1.4MHz)?
>or
>Does that mean 7.14msec (100 samples at 14kHz) after decimation?
>
>If the former, the best transition band width you can get is roughly 
>14kHz.  And, that happens to be the sample rate after decimation.  So, 
>that can't work no matter the transient which is another problem as 
>Jerry points out.
>
>If the latter, the best transition band width you can get is roughly 
>140Hz.  So that makes more sense.  And, if you figure you might only 
>need 20% of half-band transistion that would be 20% of 7kHz or 1.4kHz.
>Then the transient (and effective filter unit sample length) might be 10 
>samples and a real system could be built to do this.
>
>I'm still unclear about the "reset" though ....  ??
>
>Fred
>

The filter is supposed to be used at output of an incremental Sigma Delta
modulator. This modulator is reset once before each conversion, hence is
reset every 100 clock cycles.

Your first interpretation is true, input sampling frequency is 1.4MHz. This
is to be decimated by 100, by the filter. Output is 14kHz. I did not
understand the problem that Jerry mentioned. Can you kindly elaborate?

On 06/29/2010 03:37 PM, Fred Marshall wrote:
> analog_fever wrote:
>>> On 6/29/2010 12:38 PM, analog_fever wrote:
>>>>> On 06/29/2010 09:03 AM, analog_fever wrote:
>>>>>> I am designing filter to do decimation at the output of a Sigma
>> Delta
>>>>>> modulator. Here is the spec -
>>>>>>
>>>>>> Sampling frequency - Fs - 1.4MHz
>>>>>> Decimation factor - D - 100
>>>>>> Input - 3 bits
>>>>>> Output resolution - 13 bits.
>>>>>>
>>>>>> The filter, and the modulator are reset every 100 clock cycles.
>>>>>>
>>>>>> I tried using a CIC filter, but since it is to be reset every 100
>> clock
>>>>>> cycles, I am limited to order 1. I will not get 13 bit resolution
>> with
>>>> 1
>>>>>> order.
>>>>>>
>>>>>> I am looking at two stage filter now. The questions are
>>>>>>
>>>>>> 1. Will a 2 stage CIC work? First stage - Order 5, with decimation
>> 20,
>>>>>> Second stage - Order 4 with decimation 5, or something similar
>>>>>>
>>>>>> 2. Any pointers to two stage decimation filter design are
>> appreciated.
>>>>>> The important point is that the filter is to be reset every 100 clock
>>>>>> cycles.
>>>>>>
>
> It appears to me that this is a matter of physics perhaps not supporting
> the objective. Well, if I have the numbers right:
>
> Sample at 1.4MHz.
> Decimate by a factor of 100.
> Sample for 100 "clock" cycles.
> Does that mean 71.4usec (100 samples at 1.4MHz)?
> or
> Does that mean 7.14msec (100 samples at 14kHz) after decimation?
>
> If the former, the best transition band width you can get is roughly
> 14kHz. And, that happens to be the sample rate after decimation. So,
> that can't work no matter the transient which is another problem as
> Jerry points out.
>
> If the latter, the best transition band width you can get is roughly
> 140Hz. So that makes more sense. And, if you figure you might only need
> 20% of half-band transistion that would be 20% of 7kHz or 1.4kHz.
> Then the transient (and effective filter unit sample length) might be 10
> samples and a real system could be built to do this.
>
> I'm still unclear about the "reset" though .... ??

It is possible that there is some magic involved if the sigma-delta 
modulator is greater than 1st-order.  In this case you can still only 
resolve the signal average value to a resolution of 1% by counting ones, 
but the pattern out of the modulator will be different depending on 
where, within that 1% boundary, the average signal value lies.

Whether there is any post-modulator filtering that will cleverly extract 
the correct value to better than 1% -- I dunno.  But I do know that some 
of the TMS430 processors that TI sells have 16-bit sigma-delta ADCs that 
read out in 256 or 512 clocks or some other number that's far smaller 
than 65536 -- either they're lying through their teeth or there's 
something going on there.

Any sigma delta experts in the group?

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html

On Tue, 29 Jun 2010 11:38:30 -0500, "analog_fever"
<u...@n_o_s_p_a_m.yahoo.com> wrote:

>>On 06/29/2010 09:03 AM, analog_fever wrote:
>>> I am designing  filter to do decimation at the output of a Sigma Delta
>>> modulator. Here is the spec -
>>>
>>> Sampling frequency - Fs - 1.4MHz
>>> Decimation factor - D - 100
>>> Input - 3 bits
>>> Output resolution - 13 bits.
>>>
>>> The filter, and the modulator are reset every 100 clock cycles.
>>>
>>> I tried using a CIC filter, but since it is to be reset every 100 clock
>>> cycles, I am limited to order 1. I will not get 13 bit resolution with
>1
>>> order.
>>>
>>> I am looking at two stage filter now. The questions are
>>>
>>> 1. Will a 2 stage CIC work? First stage - Order 5, with decimation 20,
>>> Second stage - Order 4 with decimation 5, or something similar
>>>
>>> 2. Any pointers to two stage decimation filter design are appreciated.
>>>
>>> The important point is that the filter is to be reset every 100 clock
>>> cycles.
>>>
>>>
>>Why must it be reset after 100 clock cycles?
>>
>>-- 
>>
>>Tim Wescott
>>Wescott Design Services
>>http://www.wescottdesign.com
>>
>>Do you need to implement control loops in software?
>>"Applied Control Theory for Embedded Systems" was written for you.
>>See details at http://www.wescottdesign.com/actfes/actfes.html
>>
>
>That is a requirement from the modulator design. It, and the filter is to
>be reset at the start of each ADC conversion.

It is the absence of resetting that enables the sigma action to add resolution by
accumulating the residual remainders. If you reset it all regularly, you'll just get a
series of 7 bit values. While successive conversions can be averaged, the result will
never reach sigma-delta performance.
Tony

analog_fever wrote:
>> analog_fever wrote:
>>>> On 6/29/2010 12:38 PM, analog_fever wrote:
>>>>>> On 06/29/2010 09:03 AM, analog_fever wrote:
>>>>>>> I am designing  filter to do decimation at the output of a Sigma
>>> Delta
>>>>>>> modulator. Here is the spec -
>>>>>>>
>>>>>>> Sampling frequency - Fs - 1.4MHz
>>>>>>> Decimation factor - D - 100
>>>>>>> Input - 3 bits
>>>>>>> Output resolution - 13 bits.
>>>>>>>
>>>>>>> The filter, and the modulator are reset every 100 clock cycles.
>>>>>>>
>>>>>>> I tried using a CIC filter, but since it is to be reset every 100
>>> clock
>>>>>>> cycles, I am limited to order 1. I will not get 13 bit resolution
>>> with
>>>>> 1
>>>>>>> order.
>>>>>>>
>>>>>>> I am looking at two stage filter now. The questions are
>>>>>>>
>>>>>>> 1. Will a 2 stage CIC work? First stage - Order 5, with decimation
>>> 20,
>>>>>>> Second stage - Order 4 with decimation 5, or something similar
>>>>>>>
>>>>>>> 2. Any pointers to two stage decimation filter design are
>>> appreciated.
>>>>>>> The important point is that the filter is to be reset every 100
> clock
>>>>>>> cycles.
>>>>>>>
>> It appears to me that this is a matter of physics perhaps not supporting 
>> the objective.  Well, if I have the numbers right:
>>
>> Sample at 1.4MHz.
>> Decimate by a factor of 100.
>> Sample for 100 "clock" cycles.
>> Does that mean 71.4usec (100 samples at 1.4MHz)?
>> or
>> Does that mean 7.14msec (100 samples at 14kHz) after decimation?
>>
>> If the former, the best transition band width you can get is roughly 
>> 14kHz.  And, that happens to be the sample rate after decimation.  So, 
>> that can't work no matter the transient which is another problem as 
>> Jerry points out.
>>
>> If the latter, the best transition band width you can get is roughly 
>> 140Hz.  So that makes more sense.  And, if you figure you might only 
>> need 20% of half-band transistion that would be 20% of 7kHz or 1.4kHz.
>> Then the transient (and effective filter unit sample length) might be 10 
>> samples and a real system could be built to do this.
>>
>> I'm still unclear about the "reset" though ....  ??
>>
>> Fred
>>
> 
> The filter is supposed to be used at output of an incremental Sigma Delta
> modulator. This modulator is reset once before each conversion, hence is
> reset every 100 clock cycles.
> 
> Your first interpretation is true, input sampling frequency is 1.4MHz. This
> is to be decimated by 100, by the filter. Output is 14kHz. I did not
> understand the problem that Jerry mentioned. Can you kindly elaborate?

OK,

Well, first of all I'm not trying to be a sigma-delta expert in this 
thread.  I'm just trying to answer general filtering questions.  But, 
I'll try to "integrate".....

Consider a Finite Impulse Response filter (FIR filter).
An analog version would be a tapped delay line with summing weights at 
each top.
The digital version is a memory of 100 "words" that, if circularly 
addressed can be treated like a delay line.
Then, the memory contents are multiplied by the filter coefficients and 
summed.
I hope that's clear enough....

Any filter has memory of some sort and you don't get the desired 
filtering until the memory filled with data. After that, the contents of 
the filter are updated one sample at a time and the oldest data falls 
out one sample at a time.
If the input is turned "off", there's no data and the filter memory is 
empty .. or all zeros.
When you turn the input "on", it takes 100 input samples to "fill" the 
filter memory.  During that time, the summed output is in transition 
from zero output to full output - it's a "transient" and isn't generally 
useful.

So, I might imagine this:
a filter of length 100 and the idea is that it will be used for 
decimation by 100.  So, we would propose to only take each 100th sample 
at the output.

The "normal" way to do that is to simply take each 100th sample at the 
output with no reset.  Just let the new data come into the memory.

But, an equivalent way would be this:
zero out the memory.
take 100 samples.
take the summed output at that instant.
repeat.
One could do this because one is not going to use any of the interim 
output samples.
And, since one is going to wait for 100 samples, the filter is 
completely filled with new data each time.  So, there is no need to zero 
out the memory.  The entire memory gets refreshed with the new data.

Perhaps what you're thinking is that it's only necessary to *compute* 
each 100th output sample.  That means you can avoid performing 99x100 
multiplies and adds in between.  I don't think of that as a "reset".

I'm not sure that this addresses your overall design needs but I hope it 
lends insight.

Fred