Hi Group,

Is there a power dissipation model for the Viterbi decoder as a
function of the constraint length, the code rate and the operating
data rate??

I know that the answer depends on many other factors such as the
fabrication process, implemention of the Viterbi algo etc. But, I am
looking out for an emperical equation which relates the power
consumption as a function of the code parameters.

I will be grateful to if you could provide any relevant information in
this regard.

sincerely
Ramesh

Some of the TMS320C54 DSP chips will do one sysle of the Viterbi algorithm in 
a single instruction.  You might start with that.

In article <b...@posting.google.com>, 
e...@rediffmail.com (Ramesh) wrote:
>Hi Group,
>
>Is there a power dissipation model for the Viterbi decoder as a
>function of the constraint length, the code rate and the operating
>data rate??
>
>I know that the answer depends on many other factors such as the
>fabrication process, implemention of the Viterbi algo etc. But, I am
>looking out for an emperical equation which relates the power
>consumption as a function of the code parameters.
>
>I will be grateful to if you could provide any relevant information in
>this regard.
>
>sincerely
>Ramesh