I've got an idea, but for it to work, I need 3 bits transmitted (over
wireless) at a symbol rate of around 12 MHz. Is this possible?
     Would 8-psk be my best bet? 

-mw

I think, you might be better off if you use channel coding together
with higher-order alphabet.
Ex: Rate-3/4 code followed by 16-QAM. 

regards
Ramesh

Mikal wrote:
> I've got an idea, but for it to work, I need 3 bits transmitted (over
> wireless) at a symbol rate of around 12 MHz. Is this possible?
>      Would 8-psk be my best bet? 
> 
> -mw

There are few mind readers here. How many bits per symbol are there? 
What happens after the three bits are transmitted? What happens before?

If you choose a 6 GHz carrier, I don't see why there's even a question, 
so there must be important constraints you haven't mentioned.

Jerry
-- 
Engineering is the art of making what you want from things you can get.
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯

There's already an ETSI wireless standard for 8psk constellations
called 'EDGE'.  The symbol rate is around 270kHz, and the ETSI
standards body specifies EDGE receivers to handle around 5 symbols of
ISI from multipath/fading.  If your receiver faced a similar air
channel, it would need to handle over 200 symbols of ISI.  The optimal
receiver for 8psk modulation with 200 symbols of ISI is a Viterbi EQ
with 5e+179 states.  If you build such a receiver, please post your
results.

It's also not clear whether single or multi-carrier (e.g., OFDM)
modulation will be used. If you use OFDM, sure, you don't have such a
complex equalizer to implement.

Yes, I am narrowing it down.   I'm considering 16-qam.  My symbol
would consist of 4 bits @ a rate of about 3 MHz (about 12Mb/Sec). This
sounds very do-able... right?

> Yes, I am narrowing it down.   I'm considering 16-qam.  My symbol
> would consist of 4 bits @ a rate of about 3 MHz (about 12Mb/Sec).
> This sounds very do-able... right?

It will depend on the bandwidth and SNR of the air channel (and any
other air channel signal distortions, e.g. Doppler fading).

Perhaps you can tell us a bit about the application--are you designing
a mobile phone or stationary wireless LAN, etc.?

On 25 Apr 2005 11:27:54 -0700, "Mikal" <a...@hotmail.com>
wrote:

>Yes, I am narrowing it down.   I'm considering 16-qam.  My symbol
>would consist of 4 bits @ a rate of about 3 MHz (about 12Mb/Sec). This
>sounds very do-able... right?

I agree with posing questions to you as others have, like what types
of channels does this need to survive?   Indoor?  Outdoor?  What sort
of range?  Is multipath a problem?   etc., etc...

With any sort of substantive range there will probably be impairments
such as noise and multipath reflections that reduce the reliability
enough that you may need some coding for error protection.   This will
affect the net number of information bits per symbol.  e.g., with a
code of R = 1/2 you'd need to double the symbol rate to maintain the
12Mbps information rate, but the reliability will go way up.

But maybe your application doesn't care about errors.  If you provide
a bit more info then you might get more helpful answers.


Eric Jacobsen
Minister of Algorithms, Intel Corp.
My opinions may not be Intel's opinions.
http://www.ericjacobsen.org

Dang it. I wrote this whole paragraph on my application, and then lost
it! DANG...
   O.K... to summerize (with spelling errors),
My block diagram is as follows

    25 MHz serial data -> symbol formater(fpga) -> PHY ->analog front
end/TX  0>---(open air)---> then in reverse.
    What I'm at the learning curve of is... the PHY. How to format the
I&Q for the PHY. Becuase it's only 4 bits(for a total possibility of 16
patters)... would that mean that "I" (DAC) get 2 bits, and Q (DAC) gets
2 bits?   And, I can't find a whole lot on how the PHY on the recieving
end either determines where to sample the analog and at what point.

-MW

"Mikal" <a...@hotmail.com> wrote in message 
news:1...@z14g2000cwz.googlegroups.com...
> Dang it. I wrote this whole paragraph on my application, and then lost
> it! DANG...
>   O.K... to summerize (with spelling errors),
> My block diagram is as follows
>
>    25 MHz serial data -> symbol formater(fpga) -> PHY ->analog front
> end/TX  0>---(open air)---> then in reverse.
>    What I'm at the learning curve of is... the PHY. How to format the
> I&Q for the PHY. Becuase it's only 4 bits(for a total possibility of 16
> patters)... would that mean that "I" (DAC) get 2 bits, and Q (DAC) gets
> 2 bits?   And, I can't find a whole lot on how the PHY on the recieving
> end either determines where to sample the analog and at what point.
>
> -MW
>
Well if you do decide to go with 16QAM 
http://www.palgrave.com/science/engineering/otung/pdfs/07_49.pdf#search='4%20level%20gray%20code
' 
might help with some of the vocabulary.

Best of Luck - Mike