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Hi all,

Lets say I have a real signal between 0 and fi Hz (fi is much less than
fs/2) which I want to feed through a DDC but I really only want to make
use of the decimation FIR stages and not do any frequency shifting.

If I feed that signal to a DDC with the NCO tuning frequency set to 0
(lets assume that means all samples get simply multiplied by 1) then,
after the NCO (the first stage) I will simply have two identical data
streams (on the I/Q signals) which are just the sampled data from
before the NCO.

After the NCO stage there three complex decimation FIR stages.

Once I have my complex samples out the other end of the chain, how can
I recover my original, decimated signal?  I am not so sure it is as
simple as taking one of the I/Q signals and using that?

The reason for the strange setup is that the same hardware will be used
for "normal" down conversion in other modes and it would be good to
squeeze this in somehow. I am not even sure it will be possible to make
the NCO neutral but it would be intersting to hear your views.

Many thanks for your time,

Dave

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Dave said the following on 12/06/2006 16:05:
> Lets say I have a real signal between 0 and fi Hz (fi is much less than
> fs/2) which I want to feed through a DDC but I really only want to make
> use of the decimation FIR stages and not do any frequency shifting.
> 
> If I feed that signal to a DDC with the NCO tuning frequency set to 0
> (lets assume that means all samples get simply multiplied by 1) then,
> after the NCO (the first stage) I will simply have two identical data
> streams (on the I/Q signals) which are just the sampled data from
> before the NCO.

Why will they be identical?  They'll just be the real and imaginary 
parts of your signal.  Seeing as your original signal is purely real, 
the Q component will be zero, AFAICS.


> After the NCO stage there three complex decimation FIR stages.
> 
> Once I have my complex samples out the other end of the chain, how can
> I recover my original, decimated signal?  I am not so sure it is as
> simple as taking one of the I/Q signals and using that?

In this case, I think it is that simple, assuming that your decimation 
filters are phase-linear.  The Q component will still be zero.


-- 
Oli

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Hi Oli,

> > If I feed that signal to a DDC with the NCO tuning frequency set to 0
> > (lets assume that means all samples get simply multiplied by 1) then,
> > after the NCO (the first stage) I will simply have two identical data
> > streams (on the I/Q signals) which are just the sampled data from
> > before the NCO.
>
> Why will they be identical?  They'll just be the real and imaginary
> parts of your signal.  Seeing as your original signal is purely real,
> the Q component will be zero, AFAICS.

I think that when used "normally", an NCO in a DDC gets a single input
and produces the real and imaginary components from this using the
sin/cos mixers.  So, even if I define my input as being real only, if I
mix with the sin/cos multiplers using some tuning frequency I will get
two streams labelled I/Q but my original signal was not quad mixed.

This is of course academic if the NCOs multiply every sample by 1 - the
streams must be identical?

>
> > After the NCO stage there three complex decimation FIR stages.
> >
> > Once I have my complex samples out the other end of the chain, how can
> > I recover my original, decimated signal?  I am not so sure it is as
> > simple as taking one of the I/Q signals and using that?
>
> In this case, I think it is that simple, assuming that your decimation
> filters are phase-linear.  The Q component will still be zero.

Q won't be 0 however due to the NCOs multiplying everything by 1.

I would have thought that the information from my original signal would
get distributed between the I/Q outputs of the filtering stages...?

Cheers,

Dave

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Dave said the following on 13/06/2006 08:03:
>>> If I feed that signal to a DDC with the NCO tuning frequency set to 0
>>> (lets assume that means all samples get simply multiplied by 1) then,
>>> after the NCO (the first stage) I will simply have two identical data
>>> streams (on the I/Q signals) which are just the sampled data from
>>> before the NCO.
>> Why will they be identical?  They'll just be the real and imaginary
>> parts of your signal.  Seeing as your original signal is purely real,
>> the Q component will be zero, AFAICS.
> 
> I think that when used "normally", an NCO in a DDC gets a single input
> and produces the real and imaginary components from this using the
> sin/cos mixers.  So, even if I define my input as being real only, if I
> mix with the sin/cos multiplers using some tuning frequency I will get
> two streams labelled I/Q but my original signal was not quad mixed.
> 
> This is of course academic if the NCOs multiply every sample by 1 - the
> streams must be identical?

You are correct in your assumption of how a DDC operates (I think). 
However, assuming the I/Q outputs of the NCO are:

	I[n] = cos(2 pi omega n)
	Q[n] = sin(2 pi omega n)

then when omega = 0, I[n] = 1 and Q[n] = 0, for all n.  Therefore the I 
output of the DDC will just be your input signal, and the Q output will 
be zero.


-- 
Oli

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Oli Filth wrote:
> Dave said the following on 13/06/2006 08:03:
> >>> If I feed that signal to a DDC with the NCO tuning frequency set to 0
> >>> (lets assume that means all samples get simply multiplied by 1) then,
> >>> after the NCO (the first stage) I will simply have two identical data
> >>> streams (on the I/Q signals) which are just the sampled data from
> >>> before the NCO.
> >> Why will they be identical?  They'll just be the real and imaginary
> >> parts of your signal.  Seeing as your original signal is purely real,
> >> the Q component will be zero, AFAICS.
> >
> > I think that when used "normally", an NCO in a DDC gets a single input
> > and produces the real and imaginary components from this using the
> > sin/cos mixers.  So, even if I define my input as being real only, if I
> > mix with the sin/cos multiplers using some tuning frequency I will get
> > two streams labelled I/Q but my original signal was not quad mixed.
> >
> > This is of course academic if the NCOs multiply every sample by 1 - the
> > streams must be identical?
>
> You are correct in your assumption of how a DDC operates (I think).
> However, assuming the I/Q outputs of the NCO are:
>
> 	I[n] = cos(2 pi omega n)
> 	Q[n] = sin(2 pi omega n)
>
> then when omega = 0, I[n] = 1 and Q[n] = 0, for all n.  Therefore the I
> output of the DDC will just be your input signal, and the Q output will
> be zero.

A real NCO does not implement the above equations that simply.  There
is no multiply, rather there is repeated addition of the phase
increment.  So in order to get a 1 and a 0 for the real and imaginary
coefficients respectively, the phase accumulator(s) must be initialized
to phase of 0.

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Dave wrote:

> Hi all,
> 
> Lets say I have a real signal between 0 and fi Hz (fi is much less than
> fs/2) which I want to feed through a DDC but I really only want to make
> use of the decimation FIR stages and not do any frequency shifting.
> 
> If I feed that signal to a DDC with the NCO tuning frequency set to 0
> (lets assume that means all samples get simply multiplied by 1) then,
> after the NCO (the first stage) I will simply have two identical data
> streams (on the I/Q signals) which are just the sampled data from
> before the NCO.
> 
> After the NCO stage there three complex decimation FIR stages.
> 
> Once I have my complex samples out the other end of the chain, how can
> I recover my original, decimated signal?  I am not so sure it is as
> simple as taking one of the I/Q signals and using that?
> 
> The reason for the strange setup is that the same hardware will be used
> for "normal" down conversion in other modes and it would be good to
> squeeze this in somehow. I am not even sure it will be possible to make
> the NCO neutral but it would be intersting to hear your views.
> 
> Many thanks for your time,
> 
> Dave
> 

It may help to view the NCO as a phase rotator that rotates the phase 
angle of the input by a time varying phase angle.  For a fixed 
frequency, the phase angle changes at a constant rate.  With a real-only 
input, your input has no Q component, but as the NCO rotates the phase, 
it generates a complex output:

Vo = Vi * e^(-jwt+c)
    = Vi*(cos(wt+c) - j*sin(wt+c)).

So if your NCO is set up with a zero frequency, it just means that the 
phase rotation angle is constant.  If it is non-zero, you'll still get I 
and Q outputs, but they will just be the input scaled by constants equal 
to the sin and cosine of the phase angle.  If you want a real signal 
out, then force the NCO to zero phase when you set it at zero frequency, 
then the I output will be a copy of your real input at the NCO output.

The decimating filters can be treated separately from the NCO.

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I received a series of additional questions regarding this off-line 
which I am taking the liberty to bring here so that others can also 
benefit from my responses:


 >1. NCO I am talking is for clock generation made with in the FPGA using
 >a simple accumulator. It has nothing to do with frquency translation.

The NCO is simply a digital oscillator.  The frequent use is as a local
oscillator in digital wireless, and I had assumed that was what your
application was.

 >
 >2. It has to be integrated with in the CIC filter between comb and
 >integrator section.(As is done Intersil HSP50110 Digital quadrature
 >tuner chip.) Surely a good quality fir filter will be following and the
 >application is narrowband only so that CIC does not produce much
 >aliasing  and passband droops.

The CIC still has to do an integer division of the input sample rate. 
The CIC's response is the same as M cascaded boxcar filters, which are 
FIR filters with all the coefficients set to unity.  The CIC, ignoring 
the decimation for the moment, works by summing up the input samples 
then subtracting a sample N samples old from the current sum to get the 
equivalent of adding up the N samples (in other words it adds each new 
sample to a running sum, and subtracts off the old sum from N samples 
ago).  The effective filter has an integer number of taps.  The 
decimation in the CIC filter occurs ahead of the subtraction, which 
reduces the physical delay be a factor equal to the decimation ratio. 
In order to satisfy the integer number of taps, the product of the 
decimation ratio and the number of samples in the reduced delay must be 
an integer, and in order to make it realizable as a CIC, the reduced 
delay length also has to have an integer length (otherwise you'd need an 
interpolation filter).  Basically, those constraints mean that the 
decimation ratio for a CIC filter also has to be an integer.  That 
integer may be large, but the fact of the matter it still has to be an 
integer ratio.

Clock enabling the comb section is effective, and the clock enable is 
easily derived using a down counter that reloads with the decimation 
ratio-2 each time it becomes -1 (one extra bit wide means you can use 
the left most bit as the terminal count with no decoding).


 >3. Reason for using the NCO based clocking for the rest of circuit is
 >that using integer divisions of master clock one can not generate all
 >the clock rates required for  data rate configurable receivers.

you may have to add a resampler after the CIC (either before or after 
the FIR filters) in order to exactly match your required sample rate. 
The CIC alone cannot do that for you.  The resampler in your case looks 
like it is an arbitrary ratio, so you'll probably want to use a Farrow 
resampler there.  Most likely, you'll still want to use the CIC to get 
the decimated sample rate close to the desired output sample rate.

 >4. I have an opinion (may be not correct) that clock enable method
 >still consumes lot of power.

It can, however it also makes the clock logic a lot easier.  More 
importantly, using a clock-enabled approach lets you fold the dwonstream 
hardware into a bit-serial and/or sequential processing design.  That 
greatly reduces the number of gates needed for the design, and therefore 
reduces the net power consumption.  Most current FPGAs have static 
dissipation currents that are large enough that they are significant 
next to the dynamic clocking currents.  Reducing the loads on the clock 
tree by reducing the logic reduces the dynamic current linearly, and 
also reduces the static dissipation, where reducing just the clock only 
reduces the dynamic portion of the power dissipation.  The dynamic 
portion is proportional to the clock frequency.

 >5. It is well known that non integer sample rate (say M/N) change can
 >be done by interpolation followed by a decimation. For very large M and
 >N values this may become impractical. for low power devices using such
 >schemes is simply not feasible. But a NCO based CIC could be used for
 >virtually any sample rate change (No matter How large M and N values
 >are). Very strange that same performance using such a small hardware
 >complexity (and low power also) . What is missing in story? because to
 >gain something we always has to pay something. (for example to gain
 >more speed there is more  power ,more hardware etc.)

The usual implementation however is by polyphase resampling where 
mathematical tricks reconstruct the interpolation and decimation and 
using parallel sub-filter branches so that the decimation is done first 
followed by the interpolation.  This however only works where the rate 
change is a ratio of integers, and practically speaking, those integers 
need to be small.  In the general case for the type of application you 
are referring to, the resampling is not an integer or ratio of fixed 
integers ratio unless the output sample rate is determined only by the 
input sample rate (not usually the case).  You need a resampler that 
dynamically adjusts. A Farrow resampler is an example.

 >6. I have observed that narrowband receiver applications require
 >(compared to wideband ones) very tight filtering, why?

This is needed to isolate the narrowband signal from broadband noise or 
adjacent channels.  Tight filtering also means you get rid of out of 
band stuff that would cause problems when decimating to a minimum bandwidth.

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