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Discussion Groups | Comp.DSP | gut feeling

There are 4 messages in this thread.

You are currently looking at messages 0 to 4.


gut feeling - d.pal - 2006-12-24 08:32:00

Is it possible to implement 2 g729 encode+decode at 100 MHz MIPS32 core
with SDRAM as ram?


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Re: gut feeling - Vladimir Vassilevsky - 2006-12-24 10:46:00




d.pal wrote:

> Is it possible to implement 2 g729 encode+decode at 100 MHz MIPS32 core
> with SDRAM as ram?
> 

It looks possible however it may require a tough assembly coding.

Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

http://www.abvolt.com

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Re: gut feeling - Vladimir Vassilevsky - 2006-12-24 11:00:00


Vladimir Vassilevsky wrote:

> 
> 
> d.pal wrote:
> 
>> Is it possible to implement 2 g729 encode+decode at 100 MHz MIPS32 core
>> with SDRAM as ram?
>>
> 
> It looks possible however it may require a tough assembly coding.
> 

I take this back. One encoder + decoder should work, but I am doubtful 
about two encoders + decoders. Especially if you have to be 100% 
compliant with the original G.729 (not G.729a).

Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

http://www.abvolt.com


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Re: gut feeling - d.pal - 2007-01-02 23:32:00

>
>
>Vladimir Vassilevsky wrote:
>
>> 
>> 
>> d.pal wrote:
>> 
>>> Is it possible to implement 2 g729 encode+decode at 100 MHz MIPS32
core
>>> with SDRAM as ram?
>>>
>> 
>> It looks possible however it may require a tough assembly coding.
>> 
>
>I take this back. One encoder + decoder should work, but I am doubtful 
>about two encoders + decoders. Especially if you have to be 100% 
>compliant with the original G.729 (not G.729a).
>
>Vladimir Vassilevsky
>
>DSP and Mixed Signal Design Consultant
>
>http://www.abvolt.com
>
>
>

Thanks Vladimir, looks like lot of assembly coding waiting in the coming
days...by the way I was let to know half of data cache is being used as a
data buffer of sampled signals , i.e an accelerator is directly writing
samples in data cache. A hardware innovation kind of thing. :-)   

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