Hi all
       i am using TMS320C6413(500MHz).  The program have to transfer 24
lines pixels from SRAM(100MHz) each time, but the interval between the
lines is not fixed. so I need to call DAT_copy 24 times before
DAT_wait(). But there is a limit of DAT(someone name it block).  The
max number of channels DAT_copy can use is 4(Some told me). what do i
have to do?

j...@mails.tsinghua.edu.cn wrote:
> Hi all
>        i am using TMS320C6413(500MHz).  The program have to transfer 24
> lines pixels from SRAM(100MHz) each time, but the interval between the
> lines is not fixed. so I need to call DAT_copy 24 times before
> DAT_wait(). But there is a limit of DAT(someone name it block).  The
> max number of channels DAT_copy can use is 4(Some told me). what do i
> have to do?
> 

When you use DAT_copy a QDMA event is being generated.  This gets queued
up in the transfer controller.  The FIFO in the transfer controller is
16 entries deep and there are registers that control how many events a
given requestor can submit.  Since the FIFO is only 16 deep there is no
way you could submit 24 entries.  That is, you'd stall after the 16th.
Plus I would not recommend configuring the device such that the QDMA can
submit that many events anyway because other events will get stalled
which might screw up the real-time behavior of your system.

A different (probably better) option would be to use EDMA to do these
transfers.  The EDMA has 64 channels.  Assuming you have 24 unused
channels you could set up these channels to do the transfers by
appropriately programming them in the Parameter RAM (PaRAM).  To kick
off the transfer you would simply have to write to the corresonding bits
of the Event Set Register (ESR) and your transfers would run.