All-
I had posted on e2e but couldn't get anyone stirred up:
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/318557.aspx
Do you guys think it might be possible to implement this way:
1) 2 sets of functional unit pairs are running read (from x[] mem), add, and
left-rotate on write (to temp mem).
2) 2 sets of functional unit pairs are running read (from temp mem), xor and
write (to x[] mem).
Once such a pipeline is filled, I'm wondering if the effective rate can be
8 lines of C code (as shown in the e2e
post) per clock cycle.
Thanks.
-Jeff
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