Hi All, I am working on a project in which we are attempting to demod multiple (analog) FM radio stations in a FPGA. I have been trying to work out how to design the CIC / FIR filter pair in the DDC section of this design. I have a input sampling rate of 80MSPS, which undersamples a clean spectrum of 88 - 108MHz i.e. the FM band. this should give me the FM band at 8 - 28MHz with an alias at 52 - 72MHz. I then take this input and mix with a NCO generated carrier at say 20.5MHz to try to pull out one of the stations. The output of the mixer needs to then be filtered to approx 200kHz bandwidth and decimated to maybe 800kSPS? this is the part I am unsure of how to do.. I believe that I will need a CIC followed by a FIR however I am not sure the relevant paramaters of the CIC and how to set them, i.e. (decimation Rate) R = 128, but (stages)N = ?? and (differential delay)M = ??. I have read Hogenauer and still feel none the wiser.. also once the filter parameters are decided, how do you design the following FIR filter to straighten up the passband?? Anyhow, Hopefully someone out there will be able to help. Cheers, Paul Solomon
CIC Filter design for multiple FM carrier demod
Started by ●May 17, 2005
Reply by ●May 17, 20052005-05-17
Paul Solomon wrote:> Hi All, > > I am working on a project in which we are attempting to demod multiple > (analog) FM radio stations in a FPGA. > I have been trying to work out how to design the CIC / FIR filter pair in > the DDC section of this design.This paragraph has put me into abbreviation overload. FM, FPGA and FIR all make sense to me -- what do CIC and DDC mean in this context?> > I have a input sampling rate of 80MSPS, which undersamples a clean spectrum > of 88 - 108MHz i.e. the FM band. > this should give me the FM band at 8 - 28MHz with an alias at 52 - 72MHz. > > I then take this input and mix with a NCO generated carrier at say 20.5MHz > to try to pull out one of the stations. > The output of the mixer needs to then be filtered to approx 200kHz bandwidth > and decimated to maybe 800kSPS?Is it quadrature demodulation? If so 200kHz is strictly correct only if you mean -100kHz to 100kHz. You could go out more than that if you wanted to, but why?> > this is the part I am unsure of how to do.. I believe that I will need a CIC > followed by a FIR however > I am not sure the relevant paramaters of the CIC and how to set them, > i.e. (decimation Rate) R = 128, but (stages)N = ?? and (differential delay)M > = ??.Apparantly a CIC is some sort of a polyphase filter with decimation? If so, why do you need a FIR filter at all? In fact if you were clever you should be able to follow the quadrature demodulation with a single-step lowpass/decimation filter to get a nicely conditioned baseband signal that you would then have to work on to extract the FM signal.> > I have read Hogenauer and still feel none the wiser.. > > also once the filter parameters are decided, how do you design the following > FIR filter to straighten up the passband?? > > Anyhow, Hopefully someone out there will be able to help. > > Cheers, > > Paul Solomon > >-- ------------------------------------------- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Reply by ●May 17, 20052005-05-17
"Tim Wescott" <tim@seemywebsite.com> wrote in message news:118jvijkhj28t22@corp.supernews.com...> Paul Solomon wrote: > > > Hi All, > > > > I am working on a project in which we are attempting to demod multiple > > (analog) FM radio stations in a FPGA. > > I have been trying to work out how to design the CIC / FIR filter pairin> > the DDC section of this design. > > This paragraph has put me into abbreviation overload. FM, FPGA and FIR > all make sense to me -- what do CIC and DDC mean in this context?CIC - Cascaded Integrated Comb DDC - Digital Down Converter> > I have a input sampling rate of 80MSPS, which undersamples a cleanspectrum> > of 88 - 108MHz i.e. the FM band. > > this should give me the FM band at 8 - 28MHz with an alias at 52 -72MHz.> > > > I then take this input and mix with a NCO generated carrier at say20.5MHz> > to try to pull out one of the stations. > > The output of the mixer needs to then be filtered to approx 200kHzbandwidth> > and decimated to maybe 800kSPS? > > Is it quadrature demodulation? If so 200kHz is strictly correct only if > you mean -100kHz to 100kHz. You could go out more than that if you > wanted to, but why? > > > > this is the part I am unsure of how to do.. I believe that I will need aCIC> > followed by a FIR however > > I am not sure the relevant paramaters of the CIC and how to set them, > > i.e. (decimation Rate) R = 128, but (stages)N = ?? and (differentialdelay)M> > = ??. > > Apparantly a CIC is some sort of a polyphase filter with decimation? If > so, why do you need a FIR filter at all? In fact if you were clever you > should be able to follow the quadrature demodulation with a single-step > lowpass/decimation filter to get a nicely conditioned baseband signal > that you would then have to work on to extract the FM signal.A CIC is a box-car filter that (just google for lotsa references and very detailed explanations - Rick just had one of his artciles on this very topic in EE times I think) doesn't use any multipliers, supports large decimation ratios, works well in fixed point arithmentic. So these are excellent candiates for 'coarse' decimation blocks that need to be implemented in FPGAs. Since they are box-car to begin with, their frequency response is pretty bad - so they are typically followed by a FIR filter that does any 'fine' decimation that may be needed as well as correct for the amplitude droop in the pass-band caused by the CICs. Given Paul's system requirements, I would think that a single FIR (non-CIC) to get him from 80 Msps to 800ksps in one step wouldn't be easy. So he is correct in considering CICs in his design. Here is Rick's article for reference - Paul would be wise to read it before moving forward. http://www.embedded.com/showArticle.jhtml?articleID=160400592 Paul - it seems you are shooting for a decimation of about 100. I'd suggest a CIC decimation of say 64 and the rest can be handled by your final FIR. Rick's article discusses the trade-offs related to stages and differential delay choices for these filters. If you still aren't sure of what you need, ask again (with some background on what you don't get). Since the CIC filters' frequency response is known exactly, you can then create an 'inverse' of this response in the frequency domain and then perform an IFFT to get filter coeffs for your FIR filter that can correct for the CIC. Note that you probably want a combination FIR - one that will correct the CIC as well as provide filtering to remove images and good stop band attenuation for the spectrum of interest. So you'd need to combine the 2 responses together to get your filter coeffs. Cheers Bhaskar> > > > I have read Hogenauer and still feel none the wiser.. > > > > also once the filter parameters are decided, how do you design thefollowing> > FIR filter to straighten up the passband?? > > > > Anyhow, Hopefully someone out there will be able to help. > > > > Cheers, > > > > Paul Solomon > > > > > > > -- > ------------------------------------------- > Tim Wescott > Wescott Design Services > http://www.wescottdesign.com
Reply by ●May 17, 20052005-05-17
see also "Digital Signal Processing in Communication Systems" by Marvin Frerking also I would be concerned about the dynamic range of the A/D if this is a real receiver with a real antenna on the front end. Mark
Reply by ●May 17, 20052005-05-17
Bhaskar Thiagarajan wrote:> "Tim Wescott" <tim@seemywebsite.com> wrote in message > news:118jvijkhj28t22@corp.supernews.com... > >>Paul Solomon wrote: >> >> >>>Hi All, >>> >>>I am working on a project in which we are attempting to demod multiple >>>(analog) FM radio stations in a FPGA. >>>I have been trying to work out how to design the CIC / FIR filter pair > > in > >>>the DDC section of this design. >> >>This paragraph has put me into abbreviation overload. FM, FPGA and FIR >>all make sense to me -- what do CIC and DDC mean in this context? > > > CIC - Cascaded Integrated Comb > DDC - Digital Down Converter >Thanks. I've used both of these, but I forget the frigging terms. I have the unfortunate habit of inventing theory as I go along because I can think faster from first principals than I can look things up and absorb them from someone else's work (except for Detection and Estimation ala Van Trees' -- I simply cannot remember that stuff for more than a few weeks, and have to refer back to it regularly). ------------------------------------------- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Reply by ●May 17, 20052005-05-17
Mark wrote:> see also "Digital Signal Processing in Communication Systems" by Marvin > Frerking > > also I would be concerned about the dynamic range of the A/D if this is > a real receiver with a real antenna on the front end. > > Mark >That would be an interesting one to sort out -- you're certainly going to see a lot of noise averaging in this case, but you'd also see quite a bit of 3rd-order intermodulation noise. I suspect that if you're trying to compete with commercial FM receivers you wouldn't need a very impressive ADC. ------------------------------------------- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Reply by ●May 17, 20052005-05-17
Paul Solomon wrote:> Hi All, > > I am working on a project in which we are attempting to demod multiple > (analog) FM radio stations in a FPGA. > I have been trying to work out how to design the CIC / FIR filter pair in > the DDC section of this design.Does "demod multiple (analog) FM radio stations" mean several at one time (presumably with multiple outputs) or merely tune to different stations as required?> I have a input sampling rate of 80MSPS, which undersamples a clean spectrum > of 88 - 108MHz i.e. the FM band. > this should give me the FM band at 8 - 28MHz with an alias at 52 - 72MHz. > > I then take this input and mix with a NCO generated carrier at say 20.5MHz > to try to pull out one of the stations. > The output of the mixer needs to then be filtered to approx 200kHz bandwidth > and decimated to maybe 800kSPS?Maybe. I'd have to work out the numbers. Why decimate at all?> this is the part I am unsure of how to do.. I believe that I will need a CIC > followed by a FIR however > I am not sure the relevant paramaters of the CIC and how to set them, > i.e. (decimation Rate) R = 128, but (stages)N = ?? and (differential delay)M > = ??. > > I have read Hogenauer and still feel none the wiser..Hogenauer tells what and why. Rick Lyons' book, "Understanding Digital Signal Processing" tells when and how. It will make you wiser.> also once the filter parameters are decided, how do you design the following > FIR filter to straighten up the passband??It's in the book. If I wanted to look wise, I would get the book and spout it. Better you read it yourself, but if you ask nicely, ...> Anyhow, Hopefully someone out there will be able to help. > > Cheers, > > Paul SolomonLet us know how you make out. Maybe Rick will pass on some pointers. What FM demodulating scheme to you plan to use? There are a few. Jerry -- Engineering is the art of making what you want from things you can get. �����������������������������������������������������������������������
Reply by ●May 17, 20052005-05-17
"Paul Solomon" <psolomon@tpg.com.au> wrote in message news:428983ec@dnews.tpgi.com.au...> Hi All, > > I am working on a project in which we are attempting to demod multiple > (analog) FM radio stations in a FPGA. > I have been trying to work out how to design the CIC / FIR filter pair in > the DDC section of this design. > > I have a input sampling rate of 80MSPS, which undersamples a clean > spectrum of 88 - 108MHz i.e. the FM band. > this should give me the FM band at 8 - 28MHz with an alias at 52 - 72MHz. > > I then take this input and mix with a NCO generated carrier at say 20.5MHz > to try to pull out one of the stations. > The output of the mixer needs to then be filtered to approx 200kHz > bandwidth and decimated to maybe 800kSPS? > > this is the part I am unsure of how to do.. I believe that I will need a > CIC followed by a FIR however > I am not sure the relevant paramaters of the CIC and how to set them, > i.e. (decimation Rate) R = 128, but (stages)N = ?? and (differential > delay)M = ??. > > I have read Hogenauer and still feel none the wiser.. > > also once the filter parameters are decided, how do you design the > following FIR filter to straighten up the passband?? > > Anyhow, Hopefully someone out there will be able to help. > > Cheers, > > Paul Solomon >Hi Paul, There is a demo that is in the Filter Design Toolbox for MATLAB (Release 14, Service Pack 2) that may help you. The demo file is named ddcfilterchaindemo.m (see complete code below). It illustrates how to design a similar DDC system for GSM. It looks like a very similar example for what you are interested in doing (at least it could get you started). Also there is a similar "GSM Digital Downconverter" Simulink demo that ships with the Signal Processing Blockset product. Cheers, Steve Conahan Signal Processing and Communications Development The MathWorks, Inc. P.S. Here is the complete M code for the demo: %% Implementing the Filter Chain of a Digital Down-Converter in HDL % This demo uses the Filter Design Toolbox and Fixed-Point Toolbox to % design a three-stage, multirate, fixed-point filter that implements the % filter chain of a Digital Down-Converter (DDC) designed to meet the % Global System for Mobile (GSM) specification. % % Using the Filter Design HDL Coder we will generate synthesizable HDL code % for the same three-stage, multirate, fixed-point filter. Finally, using % Simulink and Link for ModelSim, we will co-simulate the fixed-point % filters to verify that the generated HDL code produces the same results % as the equivalent Simulink behavioral model. % % Note that you need all the products mentioned above to execute the % complete demo. % *<matlab:edit('ddcfilterchaindemo.m') View code for ddcfilterchaindemo>* %% Digital Down-Converter % Digital Down-Converters (DDC) are a key component of digital radios. The % DDC performs the frequency translation necessary to convert the high % input sample rates found in a digital radio, down to lower sample rates % for further and easier processing. In this example, the DDC operates at % approximately 70 MHz and must reduce the rate down to 270 KHz. % % The DDC consists of a Numeric Controlled Oscillator (NCO) and a mixer to % quadrature down convert the input signal to baseband. The baseband % signal is then low pass filtered by a Cascaded Integrator-Comb (CIC) % filter followed by two FIR decimating filters to achieve a low % sample-rate of 270 KHz ready for further processing. The final stage % often includes a resampler which interpolates or decimates the signal to % achieve the desired sample rate depending on the application. Further % filtering can also be achieved with the resampler. A block diagram of a % typical DDC is shown below. % % <<ddcdemomodel.png>> %% % This demo focuses on the three-stage, multirate, decimation filter, which % consists of a CIC and two decimating FIR filters. The CIC filter is % suitable for this high speed application (69.333 MHz) because of its % ability to achieve high decimation factors and the fact that it's % implemented without using multipliers. The CIC in this example will % perform decimation by 64. The second filter is a CIC-compensation FIR % filter (CFIR) which has an inverse-sinc passband response, and decimates % by 2. The third stage filter is a programmable FIR filter (PFIR) which % ensures that the overall filter response meets the GSM spectral mask. It % also decimates by 2 to achieve an overall decimation factor of 256. %% GSM Specifications % The GSM bandwidth of interest is 160 KHz. The GSM requirements for the % overall response of the three-stage, multirate filter of the DDC includes % decimating the input signal by 256, achieving less than 0.1 dB of % peak-to-peak passband ripple, and it must also achieve 18 dB of % attenuation at 100 KHz. The GSM out of band rejection mask is also shown % below. % % <<ddcdemogsmmask.png>> %% Cascaded Integrator-Comb (CIC) Filter % The design and cascade of the three filters can be performed via the % graphical user interface FDATool, % % <<ddcdemofdatool.png>> % % but we'll use the command line functionality. % % To avoid quantizing the fixed-point data coming from the mixer, which has % a word length of 20 bits and a fractional length of 18 bits, (S20,18), % we'll set the input word length and fractional length of the CIC to the % same values, S20,18. We must also define the word lengths per section of % the CIC. These values are chosen to avoid overflow between sections. We % define the CIC as follows: R = 64; % Decimation factor M = 1; % Differential delay N = 5; % Number of sections IWL = 20; % Input word length OWL = 20; % Input word length hcic = mfilt.cicdecim(R,M,N,IWL,OWL,[50 29 24 24 24 24 24 24 24 24]); hcic.InputFracLength = 18; %% % Let's plot and analyze the theoretical magnitude response of the CIC % filter which will operate at the input rate of 69.333 MHz. Fs_in = 69.333e6; h = fvtool(hcic,'Fs',Fs_in); set(gcf, 'Color', 'White'); %% % The first thing to note is that the CIC filter has a huge passband gain, % which is due to the additions and feedback within the structure. We can % normalize the CIC's magnitude response by cascading the CIC with a gain % that is the inverse of the gain of the CIC. Normalizing the CIC filter % response to have 0 dB gain at DC, will make it easier to analyze the % overlayed filter responses of the CIC and the next FIR filter stage. hgain = dfilt.scalar(1/gain(hcic)); % Define gain hcicnorm = cascade(hgain,hcic); % Replace the CIC in FVTool with a normalized CIC. setfilter(h,hcicnorm,'Fs',Fs_in); %% % The other thing to note is that zooming in the passband region we see % that the CIC has about -0.4 dB of attenuation (droop) at 80 KHz, which is % within the bandwidth of interest. A CIC filter is essentially a cascade % of boxcar filters and therefore has a sinc-like response which causes the % droop. This droop needs to be compensated by the FIR filter in the next % stage. axis([0 .1 -0.8 0]); %% Compensation FIR Decimator % The second stage of our DDC filter chain needs to compensate for the % passband droop caused by the CIC and decimate by 2. Since the CIC has a % sinc-like response, we can compensate for the droop with a lowpass filter % that has an inverse-sinc response in the passband. This filter will % operate at 1/64th the input sample rate which is 69.333 MHz, therefore % its rate is 1.0833MHz. The filter that meets these constraints is the % following: % Filter specifications Fs = 1.0833e6; % Sampling frequency 69.333MHz/64 N = 20; % 21 taps Npow = 5; % Sinc power w = 0.5; % Sinc frequency factor Apass = 5.7565e-4; % 0.01 dB Astop = 0.01; % 40 dB Aslope = 60; % 60 dB slope Fpass = 80e3/(Fs/2); % 80 KHz passband-edge frequency % Design filter. cfir = firceqrip(N,Fpass,[Apass,Astop],'passedge','slope',Aslope,... 'invsinc',[w,Npow]); % Define the fixed-point multirate filter. By default, the fixed-point % attributes of the accumulator and multipliers are set to ensure that full % precision arithmetic is used. hcfir = mfilt.firdecim(2,cfir); set(hcfir,... 'Arithmetic', 'fixed',... 'CoeffWordLength', 16,... 'InputWordLength', 20,... 'InputFracLength', -12); %% % Using the info method we can review the filter details in a nice format. info(hcfir) %% % Cascading the CIC with the inverse sinc filter we can see if we % eliminated the passband droop caused by the CIC. hcas1 = cascade(hcicnorm,hcfir); h = fvtool(hcicnorm,hcfir,hcas1,'Fs',[Fs_in,Fs_in/64,Fs_in]); axis([0 .1 -0.8 0.8]); legend(h,'hcic','hcfir','cascade'); set(gcf, 'Color', 'White'); %% % As we can see in the filter response of the cascade of the two filters, % which is between the CIC response and the compensating FIR response, the % passband droop has been eliminated. %% Third Stage FIR Decimator % As indicated earlier the GSM spectral mask requires an attenuation of 18 % dB at 100 KHz. So, for our third and final stage we can try a simple % equiripple lowpass filter. Once again we need to quantize the % coefficients to 16 bits. This filter also needs to decimate by 2. N = 62; % 63 taps Fs= 541666; % 541.666 kHz F = [0 80e3 100e3 Fs/2]/(Fs/2); A = [1 1 0 0]; W = [2 1]; % Weight the passband more than the stopband pfir = firgr(N,F,A,W); hpfir = mfilt.firdecim(2,pfir); set(hpfir,... 'Arithmetic', 'fixed',... 'CoeffWordLength', 16,... 'InputWordLength', 20,... 'InputFracLength', -12); %% % When defining a multirate filter by default the accumulator word size % is determined automatically to maintain full precision. However, because % we only have 20 bits for the output, let's set the output format to a % word length of 20 bits and a fractional length of -12. set(hpfir,... 'FilterInternals', 'specifyPrecision',... 'outputWordLength', 20,... 'outputFracLength',-12,... 'RoundMode', 'round',... % = nearest in SL 'OverflowMode', 'Saturate'); %% % Again we can use the info method to view the filter details. info(hpfir) %% Multistage Multirate DDC Filter Chain % Now that we have designed and quantized the three filters, we can get the % overall filter response by cascading the normalized CIC and the two FIR % filters. Again, we're using the normalized CIC filter to ensure that the % filter responses use the same scale. hcasnorm = cascade(hcicnorm,hcfir,hpfir); h = fvtool(hcasnorm,'Fs',Fs_in,'NumberofPoints',8192*3); axis([0 1 -200 10]); % Zoom-in set(gcf, 'Color', 'White'); %% % To see if the overall filter response meets the GSM specifications, we % can overlay the GSM spectral mask on the filter response. drawgsmmask; drawnow pause(3) %% % We can see that our overall filter response is within the constraints of % the GSM spectral mask. We also need to ensure that the passband ripple % meets the requirement that it is less than 0.1 dB peak-to-peak. We can % verify this by zooming in using the axis command. axis([0 .09 -0.08 0.08]); %% % Indeed the passband ripple is well below the 0.1 dB peak-to-peak GSM % requirement. %% Generate VHDL Code % FDATool also supports the generation of HDL code from the dialog shown % below. % % <<ddcdemohdldialog.png>> % % From FDATool as well as the command line you can generate VHDL or Verilog % code as well as test benches in VHDL, Verilog, or as ModelSim .do files. % Also, you have the ability to customize your generated HDL code by % specifying many options, so that the generated code meets your coding % standards and guidelines. % % However, here we will use the command line functionality to generate the % HDL code. % % Now that we have our fixed-point three-stage multirate filter meeting the % specs we are ready to generate HDL code. %% % Cascade of CIC and two FIR filters and generate VHDL. hcas = cascade(hcic,hcfir,hpfir); workingdir = tempname; generatehdl(hcas,'Name','filter','TargetLanguage','VHDL',... 'TargetDirectory',fullfile(workingdir,'hdlsrc')); %% HDL Co-simulation with ModelSim in Simulink % To verify that the generated HDL code is producing the same results as % our Simulink model, we'll use Link for ModelSim to co-simulate our HDL % code in Simulink. We have a pre-built Simulink model that includes two % signal paths. One signal path produces Simulink's behavioral model % results of the three-stage, multirate filter. The other path produces % the results of simulating, with ModelSim, the VHDL code we generated. open_system('ddcdemocosim.mdl'); %% % For the behavioral model simulation we will generate a Simulink block of % the three-stage, multirate filter we designed and place that block in the % Simulink model where we'll co-simulate with ModelSim. % Generate Simulink block of cascaded filters. Change the compensating % filter's default rounding mode because it's not supported in Simulink. set(hcfir,'FilterInternals','SpecifyPrecision','RoundMode','round'); block(hcas,'OverwriteBlock','on'); open_system('ddcdemocosim.mdl'); % Start ModelSim. cachepwd = pwd; cd(workingdir) % Go to directory where code was generated. vsim('tclstart',ddcdemolinkcmds,'socketsimulink',4449); %% % Note that the warnings above are due to the fact that the input % quantization settings are set explicity in the filter objects, but are % inherited in Simulink's filter block. % % Run Simulink simulation and open the Scope to view results. sim('ddcdemocosim'); open_system('ddcdemocosim/Verification_Results/Time Scope'); cd(cachepwd) %% % The warnings above are due to the fact that the coefficients are stored % as doubles when specified in the filter block, and therefore will be % quantized to the word length and fractional length specified in the % filter object. %% Verifying Results % The trace on the top is the excitation chirp signal. The next signal % labeled "ref" is the reference signal produced by the Simulink behavioral % model of the three-stage multirate filter. The bottom trace labeled % "cosim" on the scope is of the ModelSim simulation results of the % generated HDL code of the three-stage multirate filter. The last trace % shows the error between Simulink's behavioral model results and % ModelSim's simulation of the HDL code. %% Summary % We used several MathWorks products to design and analyze a three-stage, % multirate, fixed-point filter chain of a DDC for a GSM application. Then % we generated HDL code to implement the filter and verified the generated % code by comparing Simulink's behavioral model with HDL code simulated in % ModelSim via Link for ModelSim.
Reply by ●May 18, 20052005-05-18
Hi Bhaskar, thanks for this info, it has helped alot, and that article nicely explained the finer details of CIC that I was confused about. I am trying to do the design in matlab and am currently stalled as I do not have the fixed point toolbox that the filter design toolbox wants to do CIC filters.. I think that I have now made a correct FIR correction filter but it would be nice to be able to cascade this with a CIC filter inmatlab and see the cumulative response. So I think it will be a few days before I can report back sucsess, however I think I am on the right track now thanks to your assistance. regards, Paul Solomon "Bhaskar Thiagarajan" <bhaskart@deja.com> wrote in message news:428a1b87$0$79456$14726298@news.sunsite.dk...> "Tim Wescott" <tim@seemywebsite.com> wrote in message > news:118jvijkhj28t22@corp.supernews.com... >> Paul Solomon wrote: >> >> > Hi All, >> > >> > I am working on a project in which we are attempting to demod multiple >> > (analog) FM radio stations in a FPGA. >> > I have been trying to work out how to design the CIC / FIR filter pair > in >> > the DDC section of this design. >> >> This paragraph has put me into abbreviation overload. FM, FPGA and FIR >> all make sense to me -- what do CIC and DDC mean in this context? > > CIC - Cascaded Integrated Comb > DDC - Digital Down Converter > > >> > I have a input sampling rate of 80MSPS, which undersamples a clean > spectrum >> > of 88 - 108MHz i.e. the FM band. >> > this should give me the FM band at 8 - 28MHz with an alias at 52 - > 72MHz. >> > >> > I then take this input and mix with a NCO generated carrier at say > 20.5MHz >> > to try to pull out one of the stations. >> > The output of the mixer needs to then be filtered to approx 200kHz > bandwidth >> > and decimated to maybe 800kSPS? >> >> Is it quadrature demodulation? If so 200kHz is strictly correct only if >> you mean -100kHz to 100kHz. You could go out more than that if you >> wanted to, but why? >> > >> > this is the part I am unsure of how to do.. I believe that I will need >> > a > CIC >> > followed by a FIR however >> > I am not sure the relevant paramaters of the CIC and how to set them, >> > i.e. (decimation Rate) R = 128, but (stages)N = ?? and (differential > delay)M >> > = ??. >> >> Apparantly a CIC is some sort of a polyphase filter with decimation? If >> so, why do you need a FIR filter at all? In fact if you were clever you >> should be able to follow the quadrature demodulation with a single-step >> lowpass/decimation filter to get a nicely conditioned baseband signal >> that you would then have to work on to extract the FM signal. > > A CIC is a box-car filter that (just google for lotsa references and very > detailed explanations - Rick just had one of his artciles on this very > topic > in EE times I think) doesn't use any multipliers, supports large > decimation > ratios, works well in fixed point arithmentic. So these are excellent > candiates for 'coarse' decimation blocks that need to be implemented in > FPGAs. Since they are box-car to begin with, their frequency response is > pretty bad - so they are typically followed by a FIR filter that does any > 'fine' decimation that may be needed as well as correct for the amplitude > droop in the pass-band caused by the CICs. > > Given Paul's system requirements, I would think that a single FIR > (non-CIC) > to get him from 80 Msps to 800ksps in one step wouldn't be easy. So he is > correct in considering CICs in his design. > > Here is Rick's article for reference - Paul would be wise to read it > before > moving forward. > http://www.embedded.com/showArticle.jhtml?articleID=160400592 > > Paul - it seems you are shooting for a decimation of about 100. I'd > suggest > a CIC decimation of say 64 and the rest can be handled by your final FIR. > Rick's article discusses the trade-offs related to stages and differential > delay choices for these filters. If you still aren't sure of what you > need, > ask again (with some background on what you don't get). > > Since the CIC filters' frequency response is known exactly, you can then > create an 'inverse' of this response in the frequency domain and then > perform an IFFT to get filter coeffs for your FIR filter that can correct > for the CIC. > Note that you probably want a combination FIR - one that will correct the > CIC as well as provide filtering to remove images and good stop band > attenuation for the spectrum of interest. So you'd need to combine the 2 > responses together to get your filter coeffs. > > Cheers > Bhaskar > >> > >> > I have read Hogenauer and still feel none the wiser.. >> > >> > also once the filter parameters are decided, how do you design the > following >> > FIR filter to straighten up the passband?? >> > >> > Anyhow, Hopefully someone out there will be able to help. >> > >> > Cheers, >> > >> > Paul Solomon >> > >> > >> >> >> -- >> ------------------------------------------- >> Tim Wescott >> Wescott Design Services >> http://www.wescottdesign.com > >
Reply by ●May 18, 20052005-05-18
Hi Jerry, "Jerry Avins" <jya@ieee.org> wrote in message news:-5WdnY8J-5UwvhffRVn-tQ@rcn.net...> Paul Solomon wrote: >> Hi All, >> >> I am working on a project in which we are attempting to demod multiple >> (analog) FM radio stations in a FPGA. >> I have been trying to work out how to design the CIC / FIR filter pair in >> the DDC section of this design. > > Does "demod multiple (analog) FM radio stations" mean several at one time > (presumably with multiple outputs) or merely tune to different stations as > required?Yep, I am trying to do multiple stations at the same time, the end goal is to regenerate the set of FM carriers and retransmit, but the newer carriers will be clean. And also, I can swap the audio content of these carriers if desired!! :)> >> I have a input sampling rate of 80MSPS, which undersamples a clean >> spectrum of 88 - 108MHz i.e. the FM band. >> this should give me the FM band at 8 - 28MHz with an alias at 52 - 72MHz. >> >> I then take this input and mix with a NCO generated carrier at say >> 20.5MHz to try to pull out one of the stations. >> The output of the mixer needs to then be filtered to approx 200kHz >> bandwidth and decimated to maybe 800kSPS? > > Maybe. I'd have to work out the numbers. Why decimate at all?I believe that if you were to try and notch a 200kHz part of spectrum out when operating at 80MSPS, you need an ~ 1000 tap filter, and as I plan to do multiple channels, that means multiple 1000 tap filters. I dont think that is a good approach space wise!> >> this is the part I am unsure of how to do.. I believe that I will need a >> CIC followed by a FIR however >> I am not sure the relevant paramaters of the CIC and how to set them, >> i.e. (decimation Rate) R = 128, but (stages)N = ?? and (differential >> delay)M = ??. >> >> I have read Hogenauer and still feel none the wiser.. > > Hogenauer tells what and why. Rick Lyons' book, "Understanding Digital > Signal Processing" tells when and how. It will make you wiser. > >> also once the filter parameters are decided, how do you design the >> following FIR filter to straighten up the passband?? > > It's in the book. If I wanted to look wise, I would get the book and spout > it. Better you read it yourself, but if you ask nicely, ... > >> Anyhow, Hopefully someone out there will be able to help. >> >> Cheers, >> >> Paul Solomon > > Let us know how you make out. Maybe Rick will pass on some pointers. What > FM demodulating scheme to you plan to use? There are a few.I am unsure on the method I will use for the demod, I have read multiple approached PLL, phase detector, differentiator, etc and I was planning on implementing a few to compare performance, and then I will just go with whatever works best. Thanks for your input! Regards, Paul Solomon> > Jerry > -- > Engineering is the art of making what you want from things you can get. > �����������������������������������������������������������������������
