Dealing With Fixed Point Fractions
Fixed-point fractional math is easy to botch, and this post lays out pragmatic ways to avoid those mistakes. It clarifies the difference between integer and fractional overflow, shows how Q notation helps track binary-point scaling, and explains why multiplies add sign bits that may require shifting. Read for concrete FPGA strategies: keeping bit growth, selective shifts, or aggressive normalization, plus testing tips.
A poor man's Simulink
Markus Nentwig built a compact glue layer that embeds NGSPICE into Octave to cosimulate continuous-time circuits and digital control. The article walks through an RC lowpass example, the MEX-based Octave interface, and the breakpoint-driven cosimulation flow, showing how adaptive SPICE integration handles asynchronous and time-triggered events. It presents a practical, low-cost alternative to Simulink for tightly coupled analog-digital system design.
Finding the Best Optimum
Optimization is seductive but often misleading, especially when mathematical models don't match messy reality. Tim Wescott shares stories from circuits and communications to show how chasing the theoretical global optimum can waste time and money. He recommends framing 'best' in practical terms, validating models, and optimizing for cost and impact so products ship on time and actually work in the real world.
'z' as in 'Zorro': Frequency Masking FIR
Markus Nentwig shows an efficient way to build steep wideband FIR filters by combining upsampled and complementary stages, then masking their spectra. He provides a Matlab and Octave design program that uses a generic least-squares optimizer to place coefficients, letting you explore filter sizes and oversampling while cutting computational cost significantly compared to a conventional symmetric FIR.
Weighted least-squares FIR with shared coefficients
Markus Nentwig demonstrates how to design FIR filters that share coefficients across delay taps, allowing multiplier reuse and reduced implementation cost. He reimplements Lawson's iterative reweighted least-squares for complex-valued FIRs and provides Matlab/Octave code you can adapt for nonstandard constraints. The post explains iteration weight logic, the Toeplitz special-case with Levinson-Durbin, and practical trade-offs between multiplier count and stopband performance.
DSP Algorithm Implementation: A Comprehensive Approach
This post lays out a practical pathway for taking DSP algorithms from high level simulation to production hardware, comparing GPP, DSP, FPGA and ASIC platforms. It presents a stepwise methodology starting with nested loop programs, then exposing parallelism with data flow graphs, using SystemC transaction level modeling to bridge to Verilog or VHDL, and explains why that flow speeds design and simulation.
Fitting Filters to Measured Amplitude Response Data Using invfreqz in Matlab
This blog post has been moved to the code snippet section and can now be found HERE. Please update your bookmark. Thanks!
Knowledge Mine for Embedded Systems
A little-known interactive portal makes learning embedded systems surprisingly practical and visual. The site is organized into four main areas: embedded systems design, design lifecycle, design methods, and design tools. Each section uses clickable system block diagrams so you can jump from a block, for example a MAC unit, to a focused page with detailed explanations. It’s a handy, ready reference for DSP and embedded engineers.
Accelerating Matlab DSP Code on the GPU
Seth Benton spent a few days testing Jacket to accelerate MATLAB on NVIDIA GPUs, and found it surprisingly easy to speed up DSP code. He ran 2D FFT and interp2 benchmarks on a MacBook Air with a GeForce 9400M, seeing impressive speedups for large images while hitting GPU memory and precision limits at high sizes. The post shares practical tips on casting to GPU types, minimizing CPU-GPU transfers, and when GPU acceleration is most useful.
Of Forests and Trees and DSP
Too often DSP engineers fixate on algorithms and miss the rest of the product. Tim Wescott uses the humble Korg CA-20 chromatic tuner to show that a great algorithm alone does not make a usable device, you also need good data acquisition, adequate processing, sensible precision, a usable UI, and appropriate casing and cost. The post gives practical do's and don'ts for system-level DSP design.
Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop
This article demonstrates combining DSP and feedback-control on an Intel Cyclone floating-point FPGA to build low-latency closed-loop circuit emulators and controllers. Using a single floating-point biquad at 1.6 Msps, an IFFT multi-tone 4.096 ms capture for wideband measurement, and MATLAB references for verification, the author achieves sub-nanosecond timing insight and applies DSP phase compensation to cancel about 100 pF of PCB parasitics.
Weighted least-squares FIR with shared coefficients
Markus Nentwig demonstrates how to design FIR filters that share coefficients across delay taps, allowing multiplier reuse and reduced implementation cost. He reimplements Lawson's iterative reweighted least-squares for complex-valued FIRs and provides Matlab/Octave code you can adapt for nonstandard constraints. The post explains iteration weight logic, the Toeplitz special-case with Levinson-Durbin, and practical trade-offs between multiplier count and stopband performance.
Matlab Code to Synthesize Multiplierless FIR Filters
Learn how to build multiplierless FIR lowpass filters in Matlab using Canonic Signed-Digit coefficients. The post explains converting Parks-McClellan floating-point taps to scaled integers, then to exact CSD digits, and includes two m-files that search maintap scaling to minimize signed digits while preserving the filter response. Practical notes cover external gain compensation, the 2/3 full-scale CSD limit, and sensitivity to pass/stop edges.
Feedback Controllers - Making Hardware with Firmware. Part 5. Some FPGA Aspects.
This installment digs into practical FPGA choices and board-level issues for a low-latency, floating-point feedback controller. It compares a Cyclone V implementation against an older SHARC-based design, quantifies the tradeoff between raw DSP resources and cycle latency, and calls out Gotchas found on the BeMicro CV A9 evaluation card. Engineers get concrete prompts for where to optimize: clocking, DSP-block use, I/O standards, and algorithm partitioning.
Of Forests and Trees and DSP
Too often DSP engineers fixate on algorithms and miss the rest of the product. Tim Wescott uses the humble Korg CA-20 chromatic tuner to show that a great algorithm alone does not make a usable device, you also need good data acquisition, adequate processing, sensible precision, a usable UI, and appropriate casing and cost. The post gives practical do's and don'ts for system-level DSP design.
Knowledge Mine for Embedded Systems
A little-known interactive portal makes learning embedded systems surprisingly practical and visual. The site is organized into four main areas: embedded systems design, design lifecycle, design methods, and design tools. Each section uses clickable system block diagrams so you can jump from a block, for example a MAC unit, to a focused page with detailed explanations. It’s a handy, ready reference for DSP and embedded engineers.
DSP Algorithm Implementation: A Comprehensive Approach
This post lays out a practical pathway for taking DSP algorithms from high level simulation to production hardware, comparing GPP, DSP, FPGA and ASIC platforms. It presents a stepwise methodology starting with nested loop programs, then exposing parallelism with data flow graphs, using SystemC transaction level modeling to bridge to Verilog or VHDL, and explains why that flow speeds design and simulation.
Accelerating Matlab DSP Code on the GPU
Seth Benton spent a few days testing Jacket to accelerate MATLAB on NVIDIA GPUs, and found it surprisingly easy to speed up DSP code. He ran 2D FFT and interp2 benchmarks on a MacBook Air with a GeForce 9400M, seeing impressive speedups for large images while hitting GPU memory and precision limits at high sizes. The post shares practical tips on casting to GPU types, minimizing CPU-GPU transfers, and when GPU acceleration is most useful.
ES Week Emphasis on Component Based Design
Howdy everyone from beautiful Salzburg/Austria,
A week full of presentations on embedded systems at ESWeek was quite a mindful. Similar to most academic conferences, there was only a few papers worth taking back home to think about. Amongst these were:
1. Keynote talk by Hermann Eul from Infineon: He presented Infineon's view on SDR and its evolution. This talk was quite inspirational. However the most interesting slide on complexity of SDR evolution was removed. I wish I could give this...
'z' as in 'Zorro': Frequency Masking FIR
Markus Nentwig shows an efficient way to build steep wideband FIR filters by combining upsampled and complementary stages, then masking their spectra. He provides a Matlab and Octave design program that uses a generic least-squares optimizer to place coefficients, letting you explore filter sizes and oversampling while cutting computational cost significantly compared to a conventional symmetric FIR.
Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop
This article demonstrates combining DSP and feedback-control on an Intel Cyclone floating-point FPGA to build low-latency closed-loop circuit emulators and controllers. Using a single floating-point biquad at 1.6 Msps, an IFFT multi-tone 4.096 ms capture for wideband measurement, and MATLAB references for verification, the author achieves sub-nanosecond timing insight and applies DSP phase compensation to cancel about 100 pF of PCB parasitics.
Feedback Controllers - Making Hardware with Firmware. Part 5. Some FPGA Aspects.
This installment digs into practical FPGA choices and board-level issues for a low-latency, floating-point feedback controller. It compares a Cyclone V implementation against an older SHARC-based design, quantifies the tradeoff between raw DSP resources and cycle latency, and calls out Gotchas found on the BeMicro CV A9 evaluation card. Engineers get concrete prompts for where to optimize: clocking, DSP-block use, I/O standards, and algorithm partitioning.
DSP Algorithm Implementation: A Comprehensive Approach
This post lays out a practical pathway for taking DSP algorithms from high level simulation to production hardware, comparing GPP, DSP, FPGA and ASIC platforms. It presents a stepwise methodology starting with nested loop programs, then exposing parallelism with data flow graphs, using SystemC transaction level modeling to bridge to Verilog or VHDL, and explains why that flow speeds design and simulation.
Weighted least-squares FIR with shared coefficients
Markus Nentwig demonstrates how to design FIR filters that share coefficients across delay taps, allowing multiplier reuse and reduced implementation cost. He reimplements Lawson's iterative reweighted least-squares for complex-valued FIRs and provides Matlab/Octave code you can adapt for nonstandard constraints. The post explains iteration weight logic, the Toeplitz special-case with Levinson-Durbin, and practical trade-offs between multiplier count and stopband performance.
'z' as in 'Zorro': Frequency Masking FIR
Markus Nentwig shows an efficient way to build steep wideband FIR filters by combining upsampled and complementary stages, then masking their spectra. He provides a Matlab and Octave design program that uses a generic least-squares optimizer to place coefficients, letting you explore filter sizes and oversampling while cutting computational cost significantly compared to a conventional symmetric FIR.
Accelerating Matlab DSP Code on the GPU
Seth Benton spent a few days testing Jacket to accelerate MATLAB on NVIDIA GPUs, and found it surprisingly easy to speed up DSP code. He ran 2D FFT and interp2 benchmarks on a MacBook Air with a GeForce 9400M, seeing impressive speedups for large images while hitting GPU memory and precision limits at high sizes. The post shares practical tips on casting to GPU types, minimizing CPU-GPU transfers, and when GPU acceleration is most useful.
Fitting Filters to Measured Amplitude Response Data Using invfreqz in Matlab
This blog post has been moved to the code snippet section and can now be found HERE. Please update your bookmark. Thanks!
Of Forests and Trees and DSP
Too often DSP engineers fixate on algorithms and miss the rest of the product. Tim Wescott uses the humble Korg CA-20 chromatic tuner to show that a great algorithm alone does not make a usable device, you also need good data acquisition, adequate processing, sensible precision, a usable UI, and appropriate casing and cost. The post gives practical do's and don'ts for system-level DSP design.
Finding the Best Optimum
Optimization is seductive but often misleading, especially when mathematical models don't match messy reality. Tim Wescott shares stories from circuits and communications to show how chasing the theoretical global optimum can waste time and money. He recommends framing 'best' in practical terms, validating models, and optimizing for cost and impact so products ship on time and actually work in the real world.
Knowledge Mine for Embedded Systems
A little-known interactive portal makes learning embedded systems surprisingly practical and visual. The site is organized into four main areas: embedded systems design, design lifecycle, design methods, and design tools. Each section uses clickable system block diagrams so you can jump from a block, for example a MAC unit, to a focused page with detailed explanations. It’s a handy, ready reference for DSP and embedded engineers.
