Should DSP Undergraduate Students Study z-Transform Regions of Convergence?

Rick Lyons September 14, 201613 comments

Not long ago I presented my 3-day DSP class to a group of engineers at Tektronix Inc. in Beaverton Oregon [1]. After I finished covering my material on IIR filters' z-plane pole locations and filter stability, one of the Tektronix engineers asked a question similar to:

     "I noticed that you didn't discuss z-plane regions of      convergence here. In my undergraduate DSP class we      spent a lot of classroom and homework time on the  ...

Implementing Impractical Digital Filters

Rick Lyons July 19, 20162 comments

This blog discusses a problematic situation that can arise when we try to implement certain digital filters. Occasionally in the literature of DSP we encounter impractical digital IIR filter block diagrams, and by impractical I mean block diagrams that cannot be implemented. This blog gives examples of impractical digital IIR filters and what can be done to make them practical.

Implementing an Impractical Filter: Example 1

Reference [1] presented the digital IIR bandpass filter...

An Astounding Digital Filter Design Application

Rick Lyons July 7, 201613 comments

I've recently encountered a digital filter design application that astonished me with its design flexibility, capability, and ease of use. The software is called the "ASN Filter Designer." After experimenting with a demo version of this filter design software I was so impressed that I simply had publicize it to the subscribers here on dsprelated.com.

What I Liked About the ASN Filter Designer

With typical filter design software packages the user enters numerical values for the...

Digital PLL's -- Part 2

Neil Robertson June 15, 20165 comments

In Part 1, we found the time response of a 2nd order PLL with a proportional + integral (lead-lag) loop filter.  Now let’s look at this PLL in the Z-domain [1, 2].  We will find that the response is characterized by a loop natural frequency ωn and damping coefficient ζ. 

Having a Z-domain model of the DPLL will allow us to do three things:

Compute the values of loop filter proportional gain KL and integrator gain KI that give the desired loop natural...

The Swiss Army Knife of Digital Networks

Rick Lyons June 13, 20168 comments

This blog describes a general discrete-signal network that appears, in various forms, inside so many DSP applications. 

Figure 1 shows how the network's structure has the distinct look of a digital filter—a comb filter followed by a 2nd-order recursive network. However, I do not call this useful network a filter because its capabilities extend far beyond simple filtering. Through a series of examples I've illustrated the fundamental strength of this Swiss Army Knife of digital networks...

Digital PLL's -- Part 1

Neil Robertson June 7, 201626 comments
1. Introduction

Figure 1.1 is a block diagram of a digital PLL (DPLL).  The purpose of the DPLL is to lock the phase of a numerically controlled oscillator (NCO) to a reference signal.  The loop includes a phase detector to compute phase error and a loop filter to set loop dynamic performance.  The output of the loop filter controls the frequency and phase of the NCO, driving the phase error to zero.

One application of the DPLL is to recover the timing in a digital...

Peak to Average Power Ratio and CCDF

Neil Robertson May 17, 20164 comments

Peak to Average Power Ratio (PAPR) is often used to characterize digitally modulated signals.  One example application is setting the level of the signal in a digital modulator.  Knowing PAPR allows setting the average power to a level that is just low enough to minimize clipping.

However, for a random signal, PAPR is a statistical quantity.  We have to ask, what is the probability of a given peak power?  Then we can decide where to set the average...

Filter a Rectangular Pulse with no Ringing

Neil Robertson May 12, 201610 comments

To filter a rectangular pulse without any ringing, there is only one requirement on the filter coefficients:  they must all be positive.  However, if we want the leading and trailing edge of the pulse to be symmetrical, then the coefficients must be symmetrical.  What we are describing is basically a window function.

Consider a rectangular pulse 32 samples long with fs = 1 kHz.  Here is the Matlab code to generate the pulse:

N= 64; fs= 1000; % Hz sample...

Data Types for Control & DSP

Tim Wescott April 26, 20166 comments

There's a lot of information out there on what data types to use for digital signal processing, but there's also a lot of confusion, so the topic bears repeating.

I recently posted an entry on PID control. In that article I glossed over the data types used by showing "double" in all of my example code.  Numerically, this should work for most control problems, but it can be an extravagant use of processor resources.  There ought to be a better way to determine what precision you need...

PID Without a PhD

Tim Wescott April 26, 201612 comments

I both consult and teach in the area of digital control. Through both of these efforts, I have found that while there certainly are control problems that require all the expertise I can bring to bear, there are a great number of control problems that can be solved with the most basic knowledge of simple controllers, without resort to any formal control theory at all.

This article will tell you how to implement a simple controller in software and how to tune it without getting into heavy...

Harmonic Notch Filter

Mike March 28, 201615 comments

My basement is covered with power lines and florescent lights which makes collecting ECG and EEG data  rather difficult due to the 60 cycle hum.  I found the following notch filter to work very well at eliminating the background signal without effecting the highly amplified signals I was looking for. 

The notch filter is based on the a transfer function with the form $$H(z)=\frac{1}{2}(1+A(z))$$ where A(z) is an all pass filter. The original paper [1] describes a method to...

Resolving 'Can't initialize target CPU' on TI C6000 DSPs - Part 2

Mike Dunn November 12, 20073 comments


The previous article discussed CCS configuration. The prerequisite for the following discussion is a valid CCS configuration file. All references will be for CCS 3.3, but they may be used or adapted to other versions of CCS. From the previous discussion, we know that the configuration file is located at 'C:\CCStudio_v3.3\cc\bin\brddat\ccBrd0.dat'.

XDS510 Emulators

Initial discussion will address only XDS510 class emulators that support TI drivers and utilities. This will...

Specifying the Maximum Amplifier Noise When Driving an ADC

Rick Lyons June 9, 20148 comments

I recently learned an interesting rule of thumb regarding the use of an amplifier to drive the input of an analog to digital converter (ADC). The rule of thumb describes how to specify the maximum allowable noise power of the amplifier [1].

The Problem Here's the situation for an ADC whose maximum analog input voltage range is –VRef to +VRef. If we drive an ADC's analog input with an sine wave whose peak amplitude is VP = VRef, the ADC's output signal to noise ratio is maximized. We'll...

Complex Down-Conversion Amplitude Loss

Rick Lyons March 3, 20157 comments

This blog illustrates the signal amplitude loss inherent in a traditional complex down-conversion system. (In the literature of signal processing, complex down-conversion is also called "quadrature demodulation.")

The general idea behind complex down-conversion is shown in Figure 1(a). And the traditional hardware block diagram of a complex down-converter is shown in Figure 1(b).

Let's assume the input to our down-conversion system is an analog radio frequency (RF) signal,...

Going back to Germany!

Stephane Boucher June 13, 20176 comments

A couple of blog posts ago, I wrote that the decision to go to ESC Boston ended up being a great one for many different reasons.  I came back from the conference energized and really happy that I went.  

These feelings were amplified a few days after my return when I received an email from Rolf Segger, the founder of SEGGER Microcontroller (check out their very new website), asking if I would be interested in visiting their headquarters...

60-Hz Noise and Baseline Drift Reduction in ECG Signal Processing

Rick Lyons January 23, 20216 comments

Electrocardiogram (ECG) signals are obtained by monitoring the electrical activity of the human heart for medical diagnostic purposes [1]. This blog describes a very efficient digital filter used to reduce both 60 Hz AC power line noise and unwanted signal baseline drift that often contaminate ECG signals.


We'll first describe the ECG noise reduction filter and then examine the filter's performance in a real-world ECG signal filtering example.Proposed ECG Noise Reduction Digital...

Modeling a Continuous-Time System with Matlab

Neil Robertson June 6, 20172 comments

Many of us are familiar with modeling a continuous-time system in the frequency domain using its transfer function H(s) or H(jω).  However, finding the time response can be challenging, and traditionally involves finding the inverse Laplace transform of H(s).  An alternative way to get both time and frequency responses is to transform H(s) to a discrete-time system H(z) using the impulse-invariant transform [1,2].  This method provides an exact match to the continuous-time...

Adaptive Beamforming is like Squeezing a Water Balloon

Christopher Hogstrom January 9, 20214 comments

Adaptive beamforming was first developed in the 1960s for radar and sonar applications. The main idea is that signals can be captured using multiple sensors and the sensor outputs can be combined to enhance the signals propagating from specific directions and attenuate (null out) signals from other directions. It has grown immensely in recent years as processors have become faster and cheaper. Today, adaptive beamforming applications include smart speakers (like the Amazon Echo),...

Who else is going to Sensors Expo in San Jose? Looking for roommate(s)!

Stephane Boucher May 29, 20186 comments

This will be my first time attending this show and I must say that I am excited. I am bringing with me my cameras and other video equipment with the intention to capture as much footage as possible and produce a (hopefully) fun to watch 'highlights' video. I will also try to film as many demos as possible and share them with you.

I enjoy going to shows like this one as it gives me the opportunity to get out of my home-office (from where I manage and run the *Related sites) and actually...

Resolving 'Can't initialize target CPU' on TI C6000 DSPs - Part 1

Mike Dunn October 30, 200715 comments


Today I am going to discuss some of the basics that can help prevent errors that frustrate some users. The information is directed toward TI C6000 family DSPs, but much of it also applies to other TI DSPs. In many cases they represent the user's first involvement with using Code Composer Studio [CCS] and a target board. It has been my experience that the primary cause of the "Can't initialize target CPU" error message and similar messages like "Error connecting to...