Three Bin Exact Frequency Formulas for a Pure Complex Tone in a DFT
Cedron Dawg derives closed-form three-bin frequency estimators for a pure complex tone in a DFT using a linear algebra view that treats three adjacent bins as a vector. He shows any vector K orthogonal to [1 1 1] yields a = (K·Z)/(K·D·Z) and derives practical K choices including a Von Hann (Pascal) kernel and a data-driven projection. The post compares estimators under noise and gives simple selection rules.
Launch of Youtube Channel: My First Videos - Embedded World 2017
Stephane Boucher turned his Embedded World 2017 trip into a debut YouTube series of short booth highlight videos. He walks through the steep learning curve of trade-show filming, the specific gear he bought and rented to cope with low light and noise, and the practical mistakes he plans to fix. The post lists filmed vendors and asks readers for feedback to improve future episodes.
A Two Bin Exact Frequency Formula for a Pure Complex Tone in a DFT
Cedron Dawg derives an exact two-bin frequency formula for a pure complex tone in the DFT, eliminating amplitude and phase to isolate frequency via a complex quotient and the complex logarithm. He presents an adjacent-bin simplification that replaces a complex multiply with a bin offset plus an atan2 angle, and discusses integer-frequency handling and aliasing. C source and numerical examples show the formula working in practice.
DFT Bin Value Formulas for Pure Complex Tones
Cedron Dawg derives closed-form DFT bin formulas for single complex exponentials, eliminating the need for brute-force summation and showing how phase acts as a uniform rotation of all bins. He also gives a Dirichlet-kernel form that yields the magnitude as (M/N)|sin(δN/2)/sin(δ/2)|, explains the large-N sinc limit, and includes C code to verify the results.
Multi-Decimation Stage Filtering for Sigma Delta ADCs: Design and Optimization
A Matlab toolbox streamlines the design and optimization of multi-stage decimation filters for sigma-delta ADCs. MSD-toolbox automates stage-count and decimation-factor selection, generates Parks-McClellan equiripple FIR coefficients, and iteratively selects coefficient quantization to meet in-band noise constraints. It accepts sigma-delta bitstream stimuli for spectral and intra-stage analysis, includes cost estimation routines, and is published open-source on MathWorks with examples and a dissertation reference.
Canonic Signed Digit (CSD) Representation of Integers
Canonic Signed Digit (CSD) encoding slashes the number of nonzero bits in integer coefficients, enabling multiplierless FIR filters implemented with shifts and adds. This post uses MATLAB code to demonstrate CSD rules, show how negative values work, and plot the distribution of signed digits as bit width changes. It finishes with practical techniques to minimize signed digits per coefficient for area and power efficient filter designs.
Frequency Translation by Way of Lowpass FIR Filtering
Rick Lyons shows how you can translate a signal down in frequency and lowpass filter it in a single operation by embedding cosine mixing values into FIR coefficients. The post explains how to build the translating FIR, how to choose the number of coefficient sets, and how decimation can dramatically reduce storage needs while noting practical constraints like the requirement that ft be an integer submultiple of fs.
Minimum Shift Keying (MSK) - A Tutorial
How does MSK achieve both excellent spectral efficiency and a constant-envelope signal suitable for nonlinear amplifiers? This tutorial builds MSK step‑by‑step from binary FSK, shows the minimum frequency spacing and continuous‑phase construction, and then recasts MSK as an OQPSK (pseudo‑symbol) representation. It finishes by generalizing MSK into CP‑FSK and the wider CPM family so you can connect practical pulse shapes and modulation indices to performance.
New Video: Parametric Oscillations
Tim Wescott just posted a short new video titled "Parametric Oscillations." It’s a little off-topic for the channel, but he used the project as an excuse to break a months-long posting drought. If you follow his work, this quick update shows how small builds can rekindle momentum and prompt informal explorations of oscillation behavior.
Round Round Get Around: Why Fixed-Point Right-Shifts Are Just Fine
Jason Sachs explains why, in most embedded systems, simple bitwise right-shifts are an acceptable way to do fixed-point division rather than paying the runtime cost to round. He shows the cheap trick of adding 2^(N-1) to implement round-to-nearest, explains unbiased "round-to-even" issues, and compares arithmetic error to much larger ADC and sensor errors. The takeaway: save cycles unless your algorithm or inputs require extra precision.
DSPRelated and EmbeddedRelated now on Facebook & I will be at EE Live!
Stephane Boucher announces two practical updates for DSPRelated readers. He launched Facebook pages for DSPRelated and EmbeddedRelated so members can get faster updates, and he will be attending EE Live in San Jose from March 30 to April 3 with a $100-off promo code for early registration. He also asks the community for ideas on how to make his conference coverage most useful.
Python scipy.signal IIR Filter Design Cont.
Christopher Felton continues his practical tour of SciPy's iirdesign, moving beyond lowpass examples to show highpass, bandpass, and stopband designs with concise, code-focused explanations. He highlights how ellip and cheby2 let you tighten specifications for sharper transitions, and shows that the iirdesign workflow is consistent across filter types. Read for clear, reusable examples to produce IIR filter coefficients with scipy.signal.
Ancient History
The other day I was downloading an IDE for a new (to me) OS. When I went to compile some sample code, it failed. I went onto a forum, where I was told "if you read the release notes you'd know that the peripheral libraries are in a legacy download". Well damn! Looking back at my previous versions I realized I must have done that and forgotten about it. Everything changes, and keeping up with it takes time and effort.
When I first started with microprocessors we...
The New Forum is LIVE!
After months of hard word, I am very excited to introduce to you the new forum interface.
Here are the key features:
1- Easily add images to a post by drag & dropping the images in the editor
2- Easily attach files to a post by drag & dropping the files in the editor
3- Add latex equations to a post and they will be rendered with Mathjax (tutorial)
4- Add a code snippet and surround the code with
Instantaneous Frequency Measurement
Measuring carrier frequency quickly and with minimal data matters in radar and signal characterization. Parth Vakil explains the delay-and-multiply instantaneous frequency measurement technique, shows how analytic signals and multiple delays resolve the 2π ambiguity, and demonstrates noise, phase-wrapping, and interferer effects using MATLAB code. He also outlines practical mitigations like phase unwrapping and channelization.
Simple Discrete-Time Modeling of Lossy LC Filters
Converting a lossy LC filter into a discrete-time impulse response lets you analyze mixed analog and DSP systems in one time domain. This post walks through computing the LC frequency response via chain (ABCD) parameters including resistive losses, enforcing the Hermitian symmetry required for a real IDFT, and using the IDFT to produce an asymmetrical FIR impulse response. A 5th-order Butterworth example illustrates insertion loss and impulse-shape effects.
DFT Graphical Interpretation: Centroids of Weighted Roots of Unity
DFT bin values can be seen as centroids of weighted roots of unity, a geometric picture that makes many DFT properties immediate. Cedron Dawg uses the geometric-series identity and polar plots of integer and fractional tones to show why constants appear only at DC, how wrapping relates to bin index, and how phase, scaling, offsets, and real-signal symmetry affect bin magnitudes and angles.
Simple Concepts Explained: Fixed-Point
Fixed-point is the bridge between real-world values and integer arithmetic, and this post makes that bridge tangible with a hands-on ADC-to-gain example. It walks through mapping voltages to Q-format integers, choosing gain resolution in bits, and how multiplication adds bit growth and produces quantization error. Read it to build intuition for practical fixed-point choices when implementing DSP on FPGA or ASIC.
SEGGER's 25th Anniversary Video
Stephane Boucher spent a week at SEGGER's headquarters and distilled that visit into a tight, two-minute 25th anniversary video. The post highlights rising production value, thanks to softbox lighting and a two-camera setup that allows seamless wide-to-tight cuts and emotional close-ups. Stephane invites readers to watch full screen, leave feedback and thumbs-up on YouTube, and suggests future coverage like product launches or companies with happy engineers.
Feedback Controllers - Making Hardware with Firmware. Part 4. Engineering of Evaluation Hardware
Following on from the previous abstract descriptions of an arbitrary circuit emulation application for low-latency feedback controllers, we now come to some aspects in the hardware engineering of an evaluation design from concept to first power-up. In due course a complete specification along with application examples will be maintained on the project website.
- Part 1: Introduction
- Part 2:...
DSP Related Math: Nice Animated GIFs
Stephane Boucher collected a compact set of animated GIFs that make common DSP math click visually. He spotted popular posts on the ECE subreddit and aggregated DSP-focused GIFs in one place to speed intuition and teaching. Examples include the relationship between sin and cos with right triangles, constructing a square wave from an infinite series, and the continuous Fourier transform pair of the rect and sinc functions.
A Brief Introduction To Romberg Integration
Romberg integration delivers dramatic accuracy gains for definite integrals by combining multiple trapezoidal approximations into a single highly accurate result. Rick Lyons demonstrates how just five samples can achieve 0.0038% error versus a trapezoidal rule needing 100 samples, and a 17-sample example hits 3.6×10−4% error. The post outlines the N-segment procedure, cost scaling, and links to MATLAB code.
The 2021 DSP Online Conference
Packed with practical talks and hands-on workshops, the 2021 DSP Online Conference gives DSP engineers a quick way to refresh skills and learn new techniques. Registering grants full access to talks, workshops, and Q&A at this year's event plus instant access to last year's videos. Highlights include FIR filter design with Python, software-defined radio, convolution reviews, and DSP/ML tools for IoT, with registration discounts on request.
Feedback Controllers - Making Hardware with Firmware. Part I. Introduction
This first post kicks off a series on using DSP and feedback control with mixed-signal electronics and FPGAs to emulate two-terminal circuits and create low latency controllers. It frames circuit emulation as a feedback problem, highlights latency as the key practical constraint, and outlines the planned evaluation hardware, target devices, and software tools that will be used in later MATLAB/Simulink and FPGA work.
Adaptive Beamforming is like Squeezing a Water Balloon
Think of adaptive beamforming as squeezing a water balloon, a simple analogy that reveals how combining multiple antennas creates focused gains and deep nulls. This post walks through the MVDR (Wiener-filter–based) solution, explains steering and scanning vectors, and shows how array geometry and known signal direction control what you can and cannot cancel. Practical tips highlight limits like the N-1 interferer rule.
How Not to Reduce DFT Leakage
Rick Lyons debunks a proposed 'data-flipping' fix for DFT spectral leakage, demonstrating with MATLAB that it can produce higher sidelobes and a troubling mainlobe dip for some input frequencies. He explains that windowing's goal is to reduce amplitude discontinuities in a periodic extension, not merely to force end samples to zero, and concludes the method is frequency-dependent and not recommended.
Model a Sigma-Delta DAC Plus RC Filter
Sigma-delta digital-to-analog converters (SD DAC’s) are often used for discrete-time signals with sample rate much higher than their bandwidth. For the simplest case, the DAC output is a single bit, so the only interface hardware required is a standard digital output buffer. Because of the high sample rate relative to signal bandwidth, a very simple DAC reconstruction filter suffices, often just a one-pole RC lowpass. In this article, I present a simple Matlab function that models the combination of a basic SD DAC and one-pole RC filter. This model allows easy evaluation of the overall performance for a given input signal and choice of sample rate, R, and C.
Who else is going to Sensors Expo in San Jose? Looking for roommate(s)!
This will be my first time attending this show and I must say that I am excited. I am bringing with me my cameras and other video equipment with the intention to capture as much footage as possible and produce a (hopefully) fun to watch 'highlights' video. I will also try to film as many demos as possible and share them with you.
I enjoy going to shows like this one as it gives me the opportunity to get out of my home-office (from where I manage and run the *Related sites) and actually...
Launch of EmbeddedRelated.tv
Stephane Boucher launches EmbeddedRelated.tv to host live broadcasts from Embedded World, starting next week. The site will show a constantly evolving schedule, a Live! tab to find ongoing streams, and ad-hoc demos added from the show floor. Expect schedule conflicts and small hiccups, and plan to refresh the page and join the forum thread for real-time updates and feedback.
3 Good News
Stephane Boucher reports three quick wins for the EmbeddedRelated community: two sponsors have seeded a $1,000 rewards pool, the site now serves all pages over HTTPS, and the new forums have their first active discussions. If you want a share of the sponsor-funded rewards, jump into the forums and check the Vendors Directory for opportunities. Stay tuned for more updates.
