Implementing Impractical Digital Filters
Some published IIR block diagrams are impossible to implement because they contain delay-less feedback paths, and Rick Lyons shows how simple algebra fixes that. He works through two concrete examples—a bandpass built from a FIR notch and a narrowband notch using a feedback loop—and derives equivalent, implementable second-order IIR transfer functions. The post emphasizes spotting problematic loops and replacing them with practical block diagrams.
An Astounding Digital Filter Design Application
Rick Lyons was astonished by the ASN Filter Designer, a hands-on filter design tool that makes tweaking frequency responses as simple as dragging markers with your mouse. The software updates magnitude plots, z-plane pole/zero locations, and filter coefficients in real time, and it also includes a signal analyzer plus a MATLAB-like scripting language for custom coefficient generation. The post links to a demo and user guides so you can try it yourself.
Digital PLL's -- Part 2
Neil Robertson builds a Z-domain model of a second-order digital PLL with a proportional-plus-integral loop filter, then derives closed-form formulas for KL and KI from the desired loop natural frequency and damping. The post explains the s → (z - 1)/Ts approximation, shows how to form the closed-loop IIR CL(z) for step and frequency responses, and highlights when the linear Z-domain model falls short of nonlinear acquisition behavior.
The Swiss Army Knife of Digital Networks
This blog describes a general discrete-signal network that appears, in various forms, inside so many DSP applications.
Figure 1 shows how the network's structure has the distinct look of a digital filter—a comb filter followed by a 2nd-order recursive network. However, I do not call this useful network a filter because its capabilities extend far beyond simple filtering. Through a series of examples I've illustrated the fundamental strength of this Swiss Army Knife of digital...
Digital PLL's -- Part 1
A hands-on introduction to time-domain digital phase-locked loops, Neil Robertson builds a simple DPLL model in MATLAB and walks through the NCO, phase detector, and PI loop filter implementations. The post uses phase-in-cycles arithmetic to show how the phase accumulator, detector wrapping, and loop filter interact, and it contrasts linear steady-state behavior with the nonlinear acquisition seen when initial frequency error is large. Part 2 will cover frequency-domain tuning of the loop gains.
Peak to Average Power Ratio and CCDF
Setting digital modulator levels depends on peak-to-average power ratio, because random signals produce occasional high peaks that cause clipping. This post shows how to compute the CCDF of PAPR from a signal vector, with MATLAB code and examples for a sine wave and Gaussian noise. The examples reveal the fixed 3.01 dB PAPR of a sine and the need for large sample counts to capture rare AWGN peaks.
Filter a Rectangular Pulse with no Ringing
You can filter a rectangular pulse with no ringing simply by using an FIR whose coefficients are all positive, and make them symmetric to get identical leading and trailing edges. This post walks through a MATLAB example that convolves a normalized Hanning window with a 32-sample rectangular pulse, showing that window length controls edge duration and that shorter windows widen the spectrum. It also notes this is not a QAM pulse-shaping solution.
Data Types for Control & DSP
Control engineers often default to double precision, but Tim Wescott shows that choice can waste CPU cycles on embedded targets. He separates numeric representation into floating point, integer, and fixed-point, then walks through the tradeoffs, including quantization, overflow, and performance. A concrete PID example highlights why integrator precision and ADC scaling should drive your choice of data type rather than habit.
PID Without a PhD
You do not need control theory to implement useful PID loops in embedded projects. Tim Wescott walks through simple, ready-to-use C code, clear explanations of P, I and D terms, and a practical tuning recipe you can apply to motors, precision actuators, and heaters. The article highlights anti-windup, sampling-rate guidance, and when to call in a control expert.
Digital Envelope Detection: The Good, the Bad, and the Ugly
Envelope detection sounds simple, but implementation choices change everything. Rick Lyons gathers common digital detectors, including half-wave, full-wave, square-law, Hilbert-based complex, and synchronous coherent designs, and explains how harmonics, filtering, and carrier recovery change results. He ranks detectors by output SNR from a representative simulation and offers practical tips on filter cutoff, Hilbert transformer bandwidth, and when a simple detector is good enough.
Multi-Decimation Stage Filtering for Sigma Delta ADCs: Design and Optimization
A Matlab toolbox streamlines the design and optimization of multi-stage decimation filters for sigma-delta ADCs. MSD-toolbox automates stage-count and decimation-factor selection, generates Parks-McClellan equiripple FIR coefficients, and iteratively selects coefficient quantization to meet in-band noise constraints. It accepts sigma-delta bitstream stimuli for spectral and intra-stage analysis, includes cost estimation routines, and is published open-source on MathWorks with examples and a dissertation reference.
Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally
A practical approach to emulating lossy transmission lines in real time, using pole-zero approximations to replace irrational s-domain behaviors and enable FPGA implementation. The author shows 8-pole/zero fits for Zo(s) and a 6-pole/zero plus delay for P(s), validated against LTSpice and MATLAB. Conversion to sampled-data Zo(z) and biquad implementations is detailed, along with issues in single-precision arithmetic and mitigations such as mixed sample rates and partial-fraction decomposition.
Feedback Controllers - Making Hardware with Firmware. Part 7. Turbo-charged DSP Oscillators
You can extract high-quality, high-sample-rate sine waves from FPGAs even when floating-point units are constrained by latency. This article compares Intel's NCO IP (multiplier option) with floating-point recursive biquads on Cyclone V and Cyclone 10 GX, and explains a boosted-sample-rate technique that pushes performance toward a 48Msps DAC target. Practical measurement results, spectral data, and resource/cost trade-offs are highlighted.
Feedback Controllers - Making Hardware with Firmware. Part 3. Sampled Data Aspects
This article digs into practical sampled-data issues you must address when building feedback controllers for circuit emulation. It highlights a common MATLAB versus Simulink discrepancy caused by DAC holding, explains why FOH (ramp-invariant) c2d conversion matters, and surveys latency, bit depth, filter and precision trade-offs. It also lists candidate ADCs, DACs and FPGAs used in a real evaluation platform to guide hardware choices.
Feedback Controllers - Making Hardware with Firmware. Part 2. Ideal Model Examples
An engineer's guide to building ideal continuous-time models for hardware emulation, using TINA Spice, MATLAB and Simulink to validate controller and circuit behavior. The article shows how a passive R-C network can be emulated by an amplifier, a current measurement and a summer, with Spice, MATLAB and Simulink producing coincident Bode responses. Small phase differences between MATLAB and Simulink are noted, and sampled-data issues are slated for the next installment.
Design study: 1:64 interpolating pulse shaping FIR
Markus Nentwig presents a practical 1:64 root-raised cosine interpolator built from cascaded FIR stages that slashes computational cost. By separating pulse shaping from rate conversion, designing each interpolator to suppress only known alias bands, and equalizing the pulse shape, the design achieves just 4.69 MACs per output, roughly 12 percent of a straight polyphase implementation while meeting EVM targets.
Coupled-Form 2nd-Order IIR Resonators: A Contradiction Resolved
Rick Lyons resolves a long-standing confusion about the coupled-form 2nd-order IIR resonator by deriving its correct z-domain transfer function and explaining why textbooks can appear to contradict pole plots. He shows that with infinite precision the coupled and standard denominators match, but finite-bit quantization of rcos(Θ) and rsin(Θ) changes the z^-2 coefficient and shifts pole positions. Read to learn the correct H(z) to predict quantized behavior and when the coupled form outperforms the standard design.
DSPRelated and EmbeddedRelated now on Facebook & I will be at EE Live!
Stephane Boucher announces two practical updates for DSPRelated readers. He launched Facebook pages for DSPRelated and EmbeddedRelated so members can get faster updates, and he will be attending EE Live in San Jose from March 30 to April 3 with a $100-off promo code for early registration. He also asks the community for ideas on how to make his conference coverage most useful.
Amplitude modulation and the sampling theorem
I am working on the 11th and probably final chapter of Think DSP, which follows material my colleague Siddhartan Govindasamy developed for a class at Olin College. He introduces amplitude modulation as a clever way to sneak up on the Nyquist–Shannon sampling theorem.
Most of the code for the chapter is done: you can check it out in this IPython notebook. I haven't written the text yet, but I'll outline it here, and paste in the key...
Ancient History
The other day I was downloading an IDE for a new (to me) OS. When I went to compile some sample code, it failed. I went onto a forum, where I was told "if you read the release notes you'd know that the peripheral libraries are in a legacy download". Well damn! Looking back at my previous versions I realized I must have done that and forgotten about it. Everything changes, and keeping up with it takes time and effort.
When I first started with microprocessors we...
Discrete Wavelet Transform Filter Bank Implementation (part 2)
David Valencia walks through practical differences between the discrete wavelet transform and the discrete wavelet packet transform, showing why DWPT yields symmetric frequency resolution while DWT favors a single high-pass branch. He explains how Noble identities let you collapse multi-branch filter banks into equivalent single convolutions, then compares block convolution matrices with chain-processing and links to MATLAB code for both approaches.
Feedback Controllers - Making Hardware with Firmware. Part 2. Ideal Model Examples
An engineer's guide to building ideal continuous-time models for hardware emulation, using TINA Spice, MATLAB and Simulink to validate controller and circuit behavior. The article shows how a passive R-C network can be emulated by an amplifier, a current measurement and a summer, with Spice, MATLAB and Simulink producing coincident Bode responses. Small phase differences between MATLAB and Simulink are noted, and sampled-data issues are slated for the next installment.
Computing an FFT of Complex-Valued Data Using a Real-Only FFT Algorithm
Rick Lyons shows a compact trick to get an N-point complex FFT using only real-input FFT routines by transforming the real and imaginary parts separately and recombining their outputs. The post presents a one-line recombination formula, Xc(m) = real[Xr(m)] - imag[Xi(m)] + j{imag[Xr(m)] + real[Xi(m)]}, and an algebraic derivation based on the two-real-in-one-complex FFT identity. Useful for systems that only provide real-only FFTs.
Harmonic Notch Filter
A practical, DSP-friendly recipe for scrubbing 60 Hz power-line hum and its harmonics from noisy ECG and EEG recordings is presented, using IIR notch filters built from second-order all-pass sections. The post derives how to set all-pass phase to place notches and compute biquad coefficients by solving a simple 2x2 system, then shows C code and precomputed coefficients for cascading the first eight odd harmonics at a 2 kHz sample rate. Engineers get a compact, editable implementation with explicit control over notch bandwidth.
ESC Boston's Videos are Now Up
In my last blog, I told you about my experience at ESC Boston and the few videos that I was planning to produce and publish. Here they are, please have a look and any feedback (positive or negative) is appreciated.
Short HighlightThis is a very short (one minute) montage of some of the footage that I shot at the show & conference. In future shows, I absolutely need to insert clips here and there of engineers saying a few words about the conference (why they...
Resolving 'Can't initialize target CPU' on TI C6000 DSPs - Part 2
Mike Dunn walks through practical, low-level debugging to fix "Can't initialize target CPU" on TI C6000 DSPs using CCS 3.3, focusing on XDS510-class emulators. He demonstrates how to run xdsprobe to perform JTAG resets, read and interpret adapter and port error messages, and run JTAG IR/DR integrity tests. The article shows example outputs and a simple scope-based trace to locate signal faults.
Modeling Anti-Alias Filters
Modeling anti-alias filters brings textbook aliasing examples to life. This post shows how to build discrete-time models G(z) for analog Butterworth and Chebyshev lowpass anti-alias filters, compares bilinear transform and impulse invariance, and simulates ADC input/output including aliasing of sinusoids and Gaussian noise. It concludes that impulse invariance gives better stopband accuracy and includes Matlab helper functions.
Feedback Controllers - Making Hardware with Firmware. Part 6. Self-Calibration Related.
This article will consider the engineering of a self-calibration & self-test capability to enable the project hardware to be configured and its basic performance evaluated and verified, ready for the development of the low-latency controller DSP firmware and closed-loop applications. Performance specifications will be documented in due course, on the project website here.
- Part 6: Self-Calibration, Measurements and Signalling (this part)
- Part 5:
The Little Fruit Market: The Beginning of the Digital Explosion
A small fruit market in Mountain View became an unlikely cradle for the modern electronics era. Rick Lyons recounts how William Shockley’s lab at 391 San Antonio prompted the Traitorous Eight to form Fairchild, seeding Silicon Valley and spawning an industry whose transistor production quickly dwarfed grains of rice. The post ties that history to the everyday ubiquity of semiconductor devices.
Feedback Controllers - Making Hardware with Firmware. Part 3. Sampled Data Aspects
This article digs into practical sampled-data issues you must address when building feedback controllers for circuit emulation. It highlights a common MATLAB versus Simulink discrepancy caused by DAC holding, explains why FOH (ramp-invariant) c2d conversion matters, and surveys latency, bit depth, filter and precision trade-offs. It also lists candidate ADCs, DACs and FPGAs used in a real evaluation platform to guide hardware choices.
