A poor man's Simulink

Markus Nentwig January 24, 20153 comments

Glue between Octave and NGSPICE for discrete- and continuous time cosimulation (download) Keywords: Octave, SPICE, Simulink

Introduction

Many DSP problems have close ties with the analog world. For example, a switched-mode audio power amplifier uses a digital control loop to open and close power transistors driving an analog filter. There are commercial tools for digital-analog cosimulation: Simulink comes to mind, and mainstream EDA vendors support VHDL-AMS or Verilog-A in their...


Spline interpolation

Markus Nentwig May 11, 20146 comments

A cookbook recipe for segmented y=f(x) 3rd-order polynomial interpolation based on arbitrary input data. Includes Octave/Matlab design script and Verilog implementation example. Keywords: Spline, interpolation, function modeling, fixed point approximation, data fitting, Matlab, RTL, Verilog

Introduction

Splines describe a smooth function with a small number of parameters. They are well-known for example from vector drawing programs, or to define a "natural" movement path through given...


'z' as in 'Zorro': Frequency Masking FIR

Markus Nentwig October 2, 2012

An efficient way to implement FIR filters. Matlab / Octave example included. Keywords: Frequency masking FIR filter implementation

Introduction

An "upsampled" FIR filter uses multiple-sample delays between the taps, compared to the unity delays in a conventional FIR filter. The resulting frequency response has steeper edges, but contains periodic images along the frequency axis (Fig. 1). Due to the latter, it is typically not too useful on its own.

Figure 1: Conventional and 'upsampled'...

FIR sideways (interpolator polyphase decomposition)

Markus Nentwig September 12, 20129 comments

An efficient implementation of a symmetric-FIR polyphase 1:3 interpolator that doesn't follow the usual tapped delay line-paradigm. The example exploits the impulse response symmetry and avoids four multiplications out of 10. keywords: symmetric polyphase FIR filter implementation ASIC Matlab / Octave implementation

Introduction

An interpolating FIR filter can be implemented with a single tapped delay line, possibly going forwards and backwards for a symmetric impulse response. To...


Design of an anti-aliasing filter for a DAC

Markus Nentwig August 18, 2012
Overview
  • Octaveforge / Matlab design script. Download: here
  • weighted numerical optimization of Laplace-domain transfer function
  • linear-phase design, optimizes vector error (magnitude and phase)
  • design process calculates and corrects group delay internally
  • includes sinc() response of the sample-and-hold stage in the ADC
  • optionally includes multiplierless FIR filter
Problem Figure 1: Typical FIR-DAC-analog lowpass line-up

Digital-to-analog conversion connects digital...


TCP/IP interface (Matlab/Octave)

Markus Nentwig June 17, 201210 comments

Communicate with measurement instruments via Ethernet (no-toolbox-Matlab or Octave)

Purpose

Measurement automation is digital signal processing in a wider sense: Getting a digital signal from an analog world usually involves some measurement instruments, for example a spectrum analyzer. Modern instruments, and also many off-the-shelf prototyping boards such as FPGA cards [1] or microcontrollers [2] are able to communicate via Ethernet. Here, I provide some basic mex-functions (compiled C...


Weighted least-squares FIR with shared coefficients

Markus Nentwig May 23, 2012

FIR design with arbitrary routing between delay line and coefficient multipliers.

Includes a commented implementation of a generic IRLS FIR design algorithm.

Introduction: Reverse Engineering

While looking for numerical IIR filter optimization, a Matlab program in [1] for the design of FIR filters caught my attention. The equations looked familiar, sort of, but on closer examination the pieces refused to fit together. Without the references, it took about two evenings to sort out how it...


Instant CIC

Markus Nentwig May 8, 20124 comments

Summary:

A floating point model for a CIC decimator, including the frequency response.

Description:

A CIC filter relies on a peculiarity of its fixed-point implementation: Normal operation involves repeated internal overflows that have no effect to the output signal, as they cancel in the following stage.

One way to put it intuitively is that only the speed (and rate of change) of every little "wheel" in the clockworks carries information, but its absolute position is...


Design study: 1:64 interpolating pulse shaping FIR

Markus Nentwig December 26, 20115 comments

This article is the documentation to a code snippet that originated from a discussion on comp.dsp.

The task is to design a root-raised cosine filter with a rolloff of a=0.15 that interpolates to 64x the symbol rate at the input.

The code snippet shows a solution that is relatively straightforward to design and achieves reasonably good efficiency using only FIR filters.

Motivation: “simple solutions?”

Python number crunching faster? Part I

Christopher Felton September 17, 20114 comments

Everyone has their favorite computing platform, regardless if it is Matlab, Octave, Scilab, Mathematica, Mathcad, etc.  I have been using Python and the common numerical and scientific packages available.  Personally, I have found this to be very useful in my work.  Lately there has been some chatter on speeding up Python.

From another project I follow, MyHDL, I was introduced to the Python JIT compiler,


Feedback Controllers - Making Hardware with Firmware. Part 2. Ideal Model Examples

Steve Maslen August 24, 2017
Developing and Validating Simulation Models

This article will describe models for simulating the systems and controllers for the hardware emulation application described in Part 1 of the series.


Weighted least-squares FIR with shared coefficients

Markus Nentwig May 23, 2012

FIR design with arbitrary routing between delay line and coefficient multipliers.

Includes a commented implementation of a generic IRLS FIR design algorithm.

Introduction: Reverse Engineering

While looking for numerical IIR filter optimization, a Matlab program in [1] for the design of FIR filters caught my attention. The equations looked familiar, sort of, but on closer examination the pieces refused to fit together. Without the references, it took about two evenings to sort out how it...


ADC Clock Jitter Model, Part 1 – Deterministic Jitter

Neil Robertson April 16, 20188 comments

Analog to digital converters (ADC’s) have several imperfections that affect communications signals, including thermal noise, differential nonlinearity, and sample clock jitter [1, 2].  As shown in Figure 1, the ADC has a sample/hold function that is clocked by a sample clock.  Jitter on the sample clock causes the sampling instants to vary from the ideal sample time.  This transfers the jitter from the sample clock to the input signal.

In this article, I present a Matlab...


Plotting Discrete-Time Signals

Neil Robertson September 15, 20195 comments

A discrete-time sinusoid can have frequency up to just shy of half the sample frequency.  But if you try to plot the sinusoid, the result is not always recognizable.  For example, if you plot a 9 Hz sinusoid sampled at 100 Hz, you get the result shown in the top of Figure 1, which looks like a sine.  But if you plot a 35 Hz sinusoid sampled at 100 Hz, you get the bottom graph, which does not look like a sine when you connect the dots.  We typically want the plot of a...


'z' as in 'Zorro': Frequency Masking FIR

Markus Nentwig October 2, 2012

An efficient way to implement FIR filters. Matlab / Octave example included. Keywords: Frequency masking FIR filter implementation

Introduction

An "upsampled" FIR filter uses multiple-sample delays between the taps, compared to the unity delays in a conventional FIR filter. The resulting frequency response has steeper edges, but contains periodic images along the frequency axis (Fig. 1). Due to the latter, it is typically not too useful on its own.

Figure 1: Conventional and 'upsampled'...

Accelerating Matlab DSP Code on the GPU

Seth March 25, 20102 comments

Intrigued by GPUs, I've spent a few days testing out Jacket, an interface that lets you accelerate MATLAB (my favorite, if frustrating language) on NVIDIA GPUs. It's definitely got some caveats. But it was really easy to accelerate my code. And the results were impressive. So I thought I'd put up a few simple DSP-related benchmarks I created and ran on my laptop (a Macbook Air with NVIDIA GeForce 9400M graphics card). The m-files for the two functions I benchmarked (2D FFT and 2D...


Least-squares magic bullets? The Moore-Penrose Pseudoinverse

Markus Nentwig October 24, 20109 comments

Hello,

the topic of this brief article is a tool that can be applied to a variety of problems: The Moore-Penrose Pseudoinverse.While maybe not exactly a magic bullet, it gives us least-squares optimal solutions, and that is under many circumstances the best we can reasonably expect.

I'll demonstrate its use on a short example. More details can be found for example on Wikipedia, or the Matlab documentation...


Feedback Controllers - Making Hardware with Firmware. Part 3. Sampled Data Aspects

Steve Maslen September 9, 2017
Some Design and Simulation Considerations for Sampled-Data Controllers

This article will continue to look at some aspects of the controllers and electronics needed to create emulated physical circuits with real-world connectivity and will look at the issues that arise in sampled-data controllers compared to continuous-domain controllers. As such, is not intended as an introduction to sampled-data systems.


Part 11. Using -ve Latency DSP to Cancel Unwanted Delays in Sampled-Data Filters/Controllers

Steve Maslen June 18, 201917 comments
This final article in the series will look at -ve latency DSP and how it can be used to cancel the unwanted delays in sampled-data systems due to such factors as Nyquist filtering, ADC acquisition, DSP/FPGA algorithm computation time, DAC reconstruction and circuit propagation delays.

Some applications demand zero-latency or zero unwanted latency signal processing. Negative latency DSP may sound like the stuff of science fiction or broken physics but the arrangement as...


Compute the Frequency Response of a Multistage Decimator

Neil Robertson February 10, 20192 comments

Figure 1a shows the block diagram of a decimation-by-8 filter, consisting of a low-pass finite impulse response (FIR) filter followed by downsampling by 8 [1].  A more efficient version is shown in Figure 1b, which uses three cascaded decimate-by-two filters.  This implementation has the advantages that only FIR 1 is sampled at the highest sample rate, and the total number of filter taps is lower.

The frequency response of the single-stage decimator before downsampling is just...